R
XC3000 Series Field Programmable Gate Arrays
XC3000L IOB Switching Characteristics Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark
timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more
detailed, more precise, and more up-to-date timing information, use the values provided by the timing calculator and used
in the simulator.
Speed Grade
Symbol
-8
Description
Min
Max
Units
Propagation Delays (Input)
Pad to Direct In (I)
3
4
T
5.0
24.0
6.0
ns
ns
ns
PID
Pad to Registered In (Q) with latch transparent
Clock (IK) to Registered In (Q)
T
PTG
T
IKRI
Set-up Time (Input)
Pad to Clock (IK) set-up time
1
T
22.0
ns
PICK
Propagation Delays (Output)
Clock (OK) to Pad
same
Output (O) to Pad
same
3-state to Pad begin hi-Z
same
3-state to Pad active and valid (fast)
(fast)
(slew rate limited)
(fast)
(slew-rate limited)
(fast)
(slew-rate limited)
7
7
10
10
9
9
8
8
T
T
T
T
T
T
12.0
28.0
9.0
25.0
12.0
28.0
16.0
32.0
ns
ns
ns
ns
ns
ns
ns
ns
OKPO
OKPO
OPF
OPS
TSHZ
TSHZ
TSON
TSON
T
T
same
(slew -rate limited)
Set-up and Hold Times (Output)
Output (O) to clock (OK) set-up time
Output (O) to clock (OK) hold time
5
6
T
T
12.0
0
ns
ns
7
OOK
OKO
Clock
Clock High time
Clock Low time
Max. flip-flop toggle rate
11
12
T
T
5.0
5.0
80.0
ns
ns
MHz
IOH
IOL
F
CLK
Global Reset Delays (based on XC3042L)
RESET Pad to Registered In
RESET Pad to output pad
(Q)
(fast)
(slew-rate limited)
13
15
15
T
25.0
35.0
51.0
ns
ns
ns
RRI
T
T
RPO
RPO
Notes: 1. Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture). Typical slew rate limited output
rise/fall times are approximately four times longer.
2. Voltage levels of unused (bonded and unbonded) pads must be valid logic levels. Each can be configured with the internal
pull-up resistor or alternatively configured as a driven output or driven from an external source.
3. Input pad set-up time is specified with respect to the internal clock (ik). In order to calculate system set-up time, subtract
clock delay (pad to ik) from the input pad set-up time value. Input pad holdtime with respect to the internal clock (ik) is
negative. This means that pad level changes immediately before the internal clock edge (ik) will not be recognized.
4. TPID, TPTG, and TPICK are 3 ns higher for XTL2 when the pin is configured as a user input.
November 9, 1998 (Version 3.1)
7-51
XILINX [ XILINX, INC ]
