R
XC4000E and XC4000X Series Field Programmable Gate Arrays
Quad
Single
Double
Long
Direct
Connect
CLB
Long
Quad
Long Global Long Double Single Global Carry Direct
Clock
Clock Chain Connect
x5994
Figure 25: High-Level Routing Diagram of XC4000 Series CLB (shaded arrows indicate XC4000X only)
6
Table 14: Routing per CLB in XC4000 Series Devices
XC4000E
XC4000X
Vertical Horizontal Vertical Horizontal
Singles
Doubles
Quads
8
4
0
6
0
8
4
0
6
0
8
4
8
4
Double
Singles
Double
12
10
2
12
6
Longlines
Six Pass Transistors
Per Switch Matrix
Interconnect Point
Direct
Connects
2
Globals
Carry Logic
Total
4
2
0
0
8
1
0
0
X6600
Figure 26: Programmable Switch Matrix (PSM)
24
18
45
32
Single-Length Lines
Programmable Switch Matrices
Single-length lines provide the greatest interconnect flexi-
bility and offer fast routing between adjacent blocks. There
are eight vertical and eight horizontal single-length lines
associated with each CLB. These lines connect the switch-
ing matrices that are located in every row and a column of
CLBs.
The horizontal and vertical single- and double-length lines
intersect at a box called a programmable switch matrix
(PSM). Each switch matrix consists of programmable pass
transistors used to establish connections between the lines
(see Figure 26).
For example, a single-length signal entering on the right
side of the switch matrix can be routed to a single-length
line on the top, left, or bottom sides, or any combination
thereof, if multiple branches are required. Similarly, a dou-
ble-length signal can be routed to a double-length line on
any or all of the other three edges of the programmable
switch matrix.
Single-length lines are connected by way of the program-
mable switch matrices, as shown in Figure 28. Routing
connectivity is shown in Figure 27.
Single-length lines incur a delay whenever they go through
a switching matrix. Therefore, they are not suitable for rout-
ing signals for long distances. They are normally used to
conduct signals within a localized area and to provide the
branching for nets with fanout greater than one.
May 14, 1999 (Version 1.6)
6-29
XILINX [ XILINX, INC ]
