QPRO Family of XC1700D QML Configuration PROMs
R
Vcc
DOUT
OPTIONAL
Daisy-chained
FPGAs with
Different
configurations
OPTIONAL
Slave FPGAs
with Identical
Configurations
VCC
FPGA
MODES*
3.3V
4.7K
VPP
VCC
DATA
CLK
CE
OE/RESET
VPP
DATA
DIN
RESET
RESET
CCLK
DONE
INIT
* For mode pin connections,
refer to the appropriate FPGA data sheet.
PROM
CEO
CLK
CE
Cascaded
Serial
Memory
OE/RESET
(Low Resets the Address Pointer)
CCLK
(Output)
DIN
DOUT
(Output)
DS027_02_052200
Figure 2:
Master Serial Mode.
The one-time-programmable PROM supports automatic loading of configuration programs.
Multiple devices can be cascaded to support additional FPGAs. An early DONE inhibits the PROM data output one CCLK
cycle before the FPGA I/Os become active.
4
1-800-255-7778
DS070 (v2.1) June 1, 2000
Product Specification
XILINX [ XILINX, INC ]
