R
XC18V00 Series In-System Programmable Configuration PROMs
Table 1:
Pin Names and Descriptions
(Continued)
Pin
Name
CF
Boundary
Scan
Order
22
21
44-pin
VQFP
10
44-pin
PLCC
16
20-pin
SOIC &
PLCC
7
(1)
Function
DATA OUT
OUTPUT
ENABLE
DATA OUT
OUTPUT
ENABLE
Pin Description
Allows JTAG CONFIG instruction to
initiate FPGA configuration without
powering down FPGA. This is an
open-drain output that is pulsed Low by
the JTAG CONFIG command.
Chip Enable Output (CEO) is connected
to the CE input of the next PROM in the
chain. This output is Low when CE is Low
and OE/RESET input is High, AND the
internal address counter has been
incremented beyond its Terminal Count
(TC) value. CEO returns to High when
OE/RESET goes Low or CE goes High.
GND is the ground connection.
CEO
12
11
21
27
13
GND
TMS
MODE
SELECT
6, 18, 28 &
41
5
3, 12, 24
& 34
11
11
5
The state of TMS on the rising edge of
TCK determines the state transitions at
the Test Access Port (TAP) controller.
TMS has an internal 50K ohm resistive
pull-up on it to provide a logic “1” to the
device if the pin is not driven.
This pin is the JTAG test clock. It
sequences the TAP controller and all the
JTAG test and programming electronics.
This pin is the serial input to all JTAG
instruction and data registers. TDI has an
internal 50K ohm resistive pull-up on it to
provide a logic “1” to the system if the pin
is not driven.
This pin is the serial output for all JTAG
instruction and data registers. TDO has
an internal 50K ohm resistive pull-up on it
to provide a logic “1” to the system if the
pin is not driven.
Positive 3.3V supply voltage for internal
logic.
Positive 3.3V or 2.5V supply voltage
connected to the input buffers
(2)
and
output voltage drivers.
No connects.
TCK
CLOCK
7
13
6
TDI
DATA IN
3
9
4
TDO
DATA OUT
31
37
17
V
CCINT
V
CCO
17, 35 &
38
(3)
8, 16, 26 &
36
1, 2, 4,
11, 12, 20,
22, 23, 24,
30, 32, 33,
34, 37, 39,
44
23, 41 &
44
(3)
14, 22, 32
& 42
1, 6, 7, 8,
10, 17, 18,
26, 28, 29,
30, 36, 38,
39, 40, 43
18 & 20
(3)
19
NC
Notes:
1.
2.
3.
By default, pin 7 is the D4 pin in the 20-pin packages. However, CF --> D4 programming option can be set to override the default and route
the CF function to pin 7 in the Serial mode.
For devices with IDCODES 0502x093h, the input buffers are supplied by V
CCINT
.
For devices with IDCODES, 0503x093h, these V
CCINT
pins are no connects: pin 38 in 44-pin VQFP package, pin 44 in 44-pin PLCC
package and pin 20 in 20-pin SOIC and20-pin PLCC packages.
DS026 (v4.0) June 11, 2003
Product Specification
1-800-255-7778
3
XILINX [ XILINX, INC ]
