X9250
Figure 1. Detailed Potentiometer Block Diagram
(One of Four Arrays)
Serial Data Path
V /R
H H
Serial
Bus
Input
From Interface
Circuitry
C
o
u
n
t
Register 0
Register 2
Register 1
8
8
Parallel
Bus
Input
e
r
Wiper
Counter
Register
(WCR)
D
e
c
o
d
e
Register 3
Inc/Dec
Logic
If WCR = 00[H] then V /R = V /R
L
W
W
L
UP/DN
UP/DN
If WCR = FF[H] then V /R = V /R
H
W
W
H
V /R
L
L
Modified SCK
CLK
V
/R
W
W
Write in Process
Figure 2. Identification Byte Format
The contents of the Data Registers are saved to
nonvolatile memory when the CS pin goes from LOW
to HIGH after a complete write sequence is received
by the device. The progress of this internal write
operation can be monitored by a write in process bit
(WIP). The WIP bit is read with a read status
command.
Device Type
Identifier
0
1
0
1
0
0
A1
A0
Device Address
INSTRUCTIONS
Instruction Byte
The next byte sent to the X9250 contains the
instruction and register pointer information. The four
most significant bits are the instruction. The next four
bits point to one of the four pots and, when applicable,
they point to one of four associated registers. The
format is shown below in Figure 3.
Identification (ID) Byte
The first byte sent to the X9250 from the host,
following a CS going HIGH to LOW, is called the
Identification byte. The most significant four bits of the
slave address are a device type identifier, for the
X9250 this is fixed as 0101[B] (refer to Figure 2).
Figure 3. Instruction Byte Format
The two least significant bits in the ID byte select one
of four devices on the bus. The physical device
address is defined by the state of the A -A input pins.
Register
Select
0
1
The X9250 compares the serial data stream with the
address input state; a successful compare of both
address bits is required for the X9250 to successfully
I3
I2
I1
I0
R1 R0
P1
P0
continue the command sequence. The A –A inputs
0
1
can be actively driven by CMOS input signals or tied to
Instructions
Pot Select
V
or V .
SS
CC
The remaining two bits in the slave byte must be set to 0.
Characteristics subject to change without notice. 4 of 21
REV 1.1.5 1/31/03
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