X28HC64
WRITE CYCLE LIMITS
Symbol
t
WC(5)
t
AS
t
AH
t
CS
t
CH
t
CW
t
OES
t
OEH
t
WP
t
WPH(6)
t
DV(6)
t
DS
t
DH
t
DW(6)
t
BLC
Parameter
Write Cycle Time
Address Setup Time
Address Hold Time
Write Setup Time
Write Hold Time
CE
Pulse Width
OE
HIGH Setup Time
OE
HIGH Hold Time
WE
Pulse Width
WE
HIGH Recovery
Data Valid
Data Setup
Data Hold
Delay to Next Write
Byte Load Cycle
Min.
0
50
0
0
50
0
0
50
50
1
50
0
10
0.15
Typ.
(1)
2
Max.
5
Units
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
µs
µs
3857 PGM T11.2
100
WE
Controlled Write Cycle
tWC
ADDRESS
tAS
tCS
CE
tAH
tCH
OE
tOES
WE
tDV
DATA IN
DATA VALID
tDS
DATA OUT
HIGH Z
3857 FHD F06
tWP
tOEH
tDH
Notes:
(5) t
WC
is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum
time the device requires to automatically complete the internal write operation.
(6) t
WPH
and t
DW
are periodically sampled and not 100% tested.
13
XICOR [ XICOR INC. ]
