X28HC64
WRITE CYCLE LIMITS
(1)
Symbol
Parameter
Min.
Typ.
Max.
Units
(5)
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
Address Setup Time
Address Hold Time
Write Setup Time
Write Hold Time
CE Pulse Width
OE HIGH Setup Time
OE HIGH Hold Time
WE Pulse Width
WE HIGH Recovery
Data Valid
2
5
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
µs
WC
AS
0
50
0
AH
CS
0
CH
50
0
CW
OES
OEH
WP
WPH
0
50
50
(6)
(6)
1
DV
DS
Data Setup
50
0
Data Hold
DH
(6)
Delay to Next Write
Byte Load Cycle
10
DW
0.15
100
µs
BLC
3857 PGM T11.2
WE Controlled Write Cycle
t
WC
ADDRESS
t
t
AS
AH
t
t
CS
CH
CE
OE
t
t
OES
t
OEH
t
WP
WE
DV
DATA IN
DATA OUT
DATA VALID
DS
t
t
DH
HIGH Z
3857 FHD F06
Notes: (5) t
is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum
WC
time the device requires to automatically complete the internal write operation.
(6) t
and t
are periodically sampled and not 100% tested.
WPH
DW
13
XICOR [ XICOR INC. ]
