X28C64
WRITE CYCLE LIMITS
Symbol
(7)
(1)
Parameter
Min.
Typ.
Max.
Units
(5)
tWC
Write Cycle Time
Address Setup Time
Address Hold Time
Write Setup Time
Write Hold Time
CE Pulse Width
OE HIGH Setup Time
OE HIGH Hold Time
WE Pulse Width
WE HIGH Recovery
SDP WE Recovery
Data Valid
5
10
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
µs
tAS
0
tAH
100
0
tCS
tCH
0
tCW
tOES
tOEH
tWP
tWPH
100
10
10
100
200
1
(6)
tWPH2
tDV
tDS
tDH
tDW
1
Data Setup
50
10
10
1
Data Hold
Delay to Next Write
Byte Load Cycle
(7)
tBLC
100
µs
3853 PGM T11.1
WE Controlled Write Cycle
t
WC
ADDRESS
t
t
AH
AS
t
t
CS
CH
CE
OE
t
t
OES
t
OEH
t
WP
WE
DV
DATA IN
DATA OUT
DATA VALID
DS
t
t
DH
HIGH Z
3853 FHD F06
Notes: (5) t
is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum
WC
time the device requires to automatically complete the internal write operation.
(6) t
is the normal page write operation WE recovery time. t
is the WE recovery time needed only after the end of issuing
WPH
WPH2
the three-byte SDP command sequence and before writing the first byte of data to the array. Refer to Figure 6 which illustrates
the t requirement.
WPH2
(7) For faster t
and t
times, refer to X28HC64.
WC
BLC
13
XICOR [ XICOR INC. ]
