欢迎访问ic37.com |
会员登录 免费注册
发布采购

X24645P 参数 Datasheet PDF下载

X24645P图片预览
型号: X24645P
PDF下载: 下载PDF文件 查看货源
内容描述: 先进的2线串行é 2 PROM带座锁TM保护 [Advanced 2-Wire Serial E 2 PROM with Block Lock TM Protection]
分类和应用: 内存集成电路光电二极管可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
文件页数/大小: 18 页 / 86 K
品牌: XICOR [ XICOR INC. ]
 浏览型号X24645P的Datasheet PDF文件第3页浏览型号X24645P的Datasheet PDF文件第4页浏览型号X24645P的Datasheet PDF文件第5页浏览型号X24645P的Datasheet PDF文件第6页浏览型号X24645P的Datasheet PDF文件第8页浏览型号X24645P的Datasheet PDF文件第9页浏览型号X24645P的Datasheet PDF文件第10页浏览型号X24645P的Datasheet PDF文件第11页  
X24645  
transmits the byte. The read operation is terminated by  
the master; by not responding with an acknowledge  
and by issuing a stop condition. Refer to Figure 7 for the  
sequence of address, acknowledge and data transfer.  
READ OPERATIONS  
Read operations are initiated in the same manner as  
write operations with the exception that the R/W bit of  
the slave address is set HIGH. There are three basic  
read operations: current address read, random read  
and sequential read.  
Random Read  
Random read operations allow the master to access  
any memory location in a random manner. Prior to issu-  
ing the slave address with the R/W bit set HIGH, the  
master must first perform a “dummy” write operation.  
The master issues the start condition, and the slave ad-  
dress with the R/W bit set LOW, followed by the byte  
address it is to read. After the word address acknowl-  
edge, the master immediately reissues the start condi-  
tion and the slave address with the R/W bit set HIGH.  
This will be followed by an acknowledge from the  
X24645 and then by the data byte. The read operation  
is terminated by the master; by not responding with an  
acknowledge and by issuing a stop condition. Refer to  
Figure 8 for the address, acknowledge and data trans-  
fer sequence.  
It should be noted that the ninth clock cycle of the read  
operation is not a “don’t care.” To terminate a read op-  
eration, the master must either issue a stop condition  
during the ninth cycle or hold SDA HIGH during the  
ninth clock cycle and then issue a stop condition.  
Current Address Read  
Internally the X24645 contains an address counter that  
maintains the address of the last byte read, increment-  
ed by one or the exact address of the last byte written.  
Therefore, if the last access read was to address n, the  
next read operation would access data from address  
n + 1. Upon receipt of the slave address with the R/W  
set HIGH, the X24645 issues an acknowledge and  
Figure 7. Current Address Read  
S
T
A
R
T
S
T
O
P
SLAVE  
ADDRESS  
BUS ACTIVITY:  
MASTER  
SDA LINE  
S
P
A
C
BUS ACTIVITY:  
X24645  
DATA  
K
2783 ILL F11  
Figure 8. Random Read  
S
S
T
T
A
R
T
S
T
O
P
SLAVE  
ADDRESS  
BYTE  
ADDRESS n  
SLAVE  
ADDRESS  
A
R
T
BUS ACTIVITY:  
MASTER  
SDA LINE  
S
S
P
A
C
K
A
C
K
A
C
K
BUS ACTIVITY:  
X24645  
DATA n  
2783 ILL F12.1  
7