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X24325PM 参数 Datasheet PDF下载

X24325PM图片预览
型号: X24325PM
PDF下载: 下载PDF文件 查看货源
内容描述: 先进的2线串行é 2 PROM带座锁TM保护 [Advanced 2-Wire Serial E 2 PROM with Block Lock TM Protection]
分类和应用: 存储内存集成电路光电二极管可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
文件页数/大小: 17 页 / 81 K
品牌: XICOR [ XICOR INC. ]
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X24325
READ OPERATIONS
Read operations are initiated in the same manner as
write operations with the exception that the R/W bit of
the slave address is set HIGH. There are three basic
read operations: current address read, random read
and sequential read.
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read op-
eration, the master must either issue a stop condition
during the ninth cycle or hold SDA HIGH during the
ninth clock cycle and then issue a stop condition.
Current Address Read
Internally the X24325 contains an address counter that
maintains the address of the last word read, increment-
ed by one or the exact address of the last word written.
Therefore, if the last access read was to address n, the
next read operation would access data from address
n + 1. Upon receipt of the slave address with the R/W
set HIGH, the X24325 issues an acknowledge and
transmits the eight-bit word. The read operation is ter-
minated by the master; by not responding with an ac-
knowledge and by issuing a stop condition. Refer to
Figure 7 for the sequence of address, acknowledge
and data transfer.
Random Read
Random read operations allow the master to access
any memory location in a random manner. Prior to issu-
ing the slave address with the R/W bit set HIGH, the
master must first perform a “dummy” write operation.
The master issues the start condition, and the slave ad-
dress with the R/W bit set LOW, followed by the word
address it is to read. After the word address acknowl-
edge, the master immediately reissues the start condi-
tion and the slave address with the R/W bit set HIGH.
This will be followed by an acknowledge from the
X24325 and then by the eight-bit word. The read oper-
ation is terminated by the master; by not responding
with an acknowledge and by issuing a stop condition.
Refer to Figure 8 for the address, acknowledge and
data transfer sequence.
Figure 7. Current Address Read
S
T
A
R
T
S
A
C
K
DATA
6552 ILL F11
BUS ACTIVITY:
MASTER
SDA LINE
BUS ACTIVITY:
X24325
SLAVE
ADDRESS
S
T
O
P
P
Figure 8. Random Read
S
T
A
R
T
S
A
C
K
A
C
K
S
T
A
R
T
S
A
C
K
DATA n
6552 ILL F12.1
BUS ACTIVITY:
MASTER
SDA LINE
BUS ACTIVITY:
X24325
SLAVE
ADDRESS
WORD
ADDRESS n
SLAVE
ADDRESS
S
T
O
P
P
7