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X24164P 参数 Datasheet PDF下载

X24164P图片预览
型号: X24164P
PDF下载: 下载PDF文件 查看货源
内容描述: 串行E2PROM [Serial E2PROM]
分类和应用: 存储内存集成电路光电二极管可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
文件页数/大小: 14 页 / 62 K
品牌: XICOR [ XICOR INC. ]
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X24164
DEVICE ADDRESSING
Following a start condition the master must output the
address of the slave it is accessing. The most significant
bit of the slave is a one (see Figure 4). The next three bits
are the device select bits. A system could have up to
eight X24164’s on the bus. The eight addresses are
defined by the state of the S
0
,
S
1
, and S
2
inputs. S
1
of the
slave address must be the inverse of the
S
1
input pin.
Figure 4. Slave Address
HIGH
ORDER
WORD
ADDRESS
The last bit of the slave address defines the operation to
be performed. When set to one a read operation is
selected, when set to zero a write operation is selected.
Following the start condition, the X24164 monitors the
SDA bus comparing the slave address being transmit-
ted with its slave address device type identifier. Upon a
correct compare the X24164 outputs an acknowledge
on the SDA line. Depending on the state of the R/W bit,
the X24164 will execute a read or write operation.
WRITE OPERATIONS
Byte Write
For a write operation, the X24164 requires a second
address field. This address field is the word address,
comprised of eight bits, providing access to any one of
2048 words in the array. Upon receipt of the word
address the X24164 responds with an acknowledge,
and awaits the next eight bits of data, again responding
with an acknowledge. The master then terminates the
transfer by generating a stop condition, at which time the
X24164 begins the internal write cycle to the nonvolatile
memory. While the internal write cycle is in progress the
X24164 inputs are disabled, and the device will not
respond to any requests from the master. Refer to
Figure 5 for the address, acknowledge and data transfer
sequence.
DEVICE
SELECT
1
S2
S1
S0
A2
A1
A0
R/W
3846 FHD F10
The next three bits of the slave address are an extension
of the array’s address and are concatenated with the
eight bits of address in the word address field, providing
direct access to the whole 2048 x 8 array.
Figure 5. Byte Write
S
T
A
BUS ACTIVITY:
R
MASTER
T
SDA LINE
BUS ACTIVITY:
X24164
S
A
C
K
SLAVE
ADDRESS
WORD
ADDRESS
DATA
S
T
O
P
P
A
C
K
A
C
K
3846 FHD F11
5