X24164
Bus Timing
t
t
t
R
t
HIGH
LOW
F
SCL
t
t
t
t
t
SU:STO
SU:STA
HD:STA
HD:DAT
SU:DAT
SDA IN
t
t
t
AA
DH
BUF
SDA OUT
3846 FHD F05
Write Cycle Limits
Symbol
(5)
Parameter
Write Cycle Time
Min.
Typ.
Max.
Units
(6)
TWR
5
10
ms
3846 PGM T09
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
erase/programcycle.Duringthewritecycle,theX24164
bus interface circuits are disabled, SDA is allowed to
remainhigh,andthedevicedoesnotrespondtoitsslave
address.
Write Cycle Timing
SCL
ACK
SDA
8th BIT
WORD n
t
WR
STOP
CONDITION
START
CONDITION
3846 FHD F06
Notes: (5) Typical values are for T = 25°C and nominal supply voltage (5V).
A
(6) tWR is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum
time the device requires to automatically complete the internal write operation.
Guidelines for Calculating Typical Values of
Bus Pull-Up Resistors
SYMBOL TABLE
WAVEFORM
INPUTS
OUTPUTS
120
V
CC MAX
R
=
=1.8KΩ
Must be
steady
Will be
steady
MIN
I
100
80
OL MIN
t
R
R
=
May change
from Low to
High
Will change
from Low to
High
MAX
C
BUS
MAX.
60
40
20
0
RESISTANCE
May change
from High to
Low
Will change
from High to
Low
MIN.
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
RESISTANCE
20 40 60 80
120
100
0
Center Line
is High
Impedance
N/A
BUS CAPACITANCE (pF)
3846 FHD F18
11
XICOR [ XICOR INC. ]
