欢迎访问ic37.com |
会员登录 免费注册
发布采购

X24042S8M-3 参数 Datasheet PDF下载

X24042S8M-3图片预览
型号: X24042S8M-3
PDF下载: 下载PDF文件 查看货源
内容描述: 串行E2PROM [Serial E2PROM]
分类和应用: 可编程只读存储器
文件页数/大小: 15 页 / 64 K
品牌: XICOR [ XICOR INC. ]
 浏览型号X24042S8M-3的Datasheet PDF文件第1页浏览型号X24042S8M-3的Datasheet PDF文件第2页浏览型号X24042S8M-3的Datasheet PDF文件第3页浏览型号X24042S8M-3的Datasheet PDF文件第4页浏览型号X24042S8M-3的Datasheet PDF文件第6页浏览型号X24042S8M-3的Datasheet PDF文件第7页浏览型号X24042S8M-3的Datasheet PDF文件第8页浏览型号X24042S8M-3的Datasheet PDF文件第9页  
X24042  
DEVICE ADDRESSING  
The last bit of the slave address defines the operation to  
be performed. When set to one a read operation is  
selected, when set to zero a write operation is selected.  
Following a start condition the master must output the  
address of the slave it is accessing. The most significant  
four bits of the slave address are the device type  
identifier (see Figure 4). For the X24042 this is fixed as  
1010[B].  
Following the start condition, the X24042 monitors the  
SDA bus comparing the slave address being transmit-  
ted with its slave address (device type and state of the  
A2 and A1 inputs). Upon a correct compare the X24042  
outputs an acknowledge on the SDA line. Depending on  
the state of the R/W bit, the X24042 will execute a read  
or write operation.  
Figure 4. Slave Address  
HIGH  
ORDER  
DEVICE TYPE  
IDENTIFIER  
WORD  
ADDRESS  
WRITE OPERATIONS  
Byte Write  
1
0
1
0
A2  
A1  
A0 R/W  
For a write operation, the X24042 requires a second  
address field. This address field is the word address,  
comprised of eight bits, providing access to any one of  
the 512 words in the selected page of memory. Upon  
receipt of the word address the X24042 responds with  
an acknowledge, and awaits the next eight bits of data,  
again responding with an acknowledge. The master  
then terminates the transfer by generating a stop condi-  
tion, at which time the X24042 begins the internal write  
cycle to the nonvolatile memory. While the internal write  
cycle is in progress the X24042 inputs are disabled, and  
the device will not respond to any requests from the  
master. Refer to Figure 5 for the address, acknowledge  
and data transfer sequence.  
DEVICE  
ADDRESS  
3849 FHD F09  
The next two significant bits addresses a particular  
device. A system could have up to four X24042 devices  
on the bus (see Figure 10). The four addresses are  
defined by the state of the A1 and A2 input.  
The next bit of the slave address is an extension of the  
array’s address and is concatenated with the eight bits  
of address in the word address field, providing direct  
access to the whole 512 x 8 array.  
Figure 5. Byte Write  
S
T
S
SLAVE  
ADDRESS  
WORD  
ADDRESS  
A
R
T
T
BUS ACTIVITY:  
MASTER  
DATA  
O
P
SDA LINE  
S
P
A
C
K
A
C
K
A
C
K
BUS ACTIVITY:  
X24042  
3849 FHD F10  
5
 复制成功!