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X24026Y 参数 Datasheet PDF下载

X24026Y图片预览
型号: X24026Y
PDF下载: 下载PDF文件 查看货源
内容描述: 串行E2PROM [Serial E2PROM]
分类和应用: 存储内存集成电路可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
文件页数/大小: 15 页 / 67 K
品牌: XICOR [ XICOR INC. ]
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X24026  
WRITE CYCLE LIMITS  
(5)  
Typ.  
Symbol  
Parameter  
Min.  
Max.  
Units  
(6)  
t
Write Cycle Time  
5
10  
ms  
WR  
7020 FRM T08  
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal erase/program  
cycle. During the write cycle, the X24026 bus interface circuits are disabled, SDA is allowed to remain high, and the  
device does not respond to its slave address.  
Write Cycle Timing  
SCL  
ACK  
SDA  
8th BIT  
WORD n  
t
WR  
STOP  
CONDITION  
START  
CONDITION  
X24026  
ADDRESS  
7020 FRM 15  
Notes: (5) Typical values are for T = 25°C and nominal supply voltage (5V)  
A
(6) t  
is the minimum cycle time from the system perspective when polling techniques are not used. It is the maximum time the device  
WR  
requires to perform the internal write operation.  
Guidelines for Calculating Typical Values of Bus  
Pull-Up Resistors  
SYMBOL TABLE  
WAVEFORM  
INPUTS  
OUTPUTS  
120  
VCC MAX  
IOL MIN  
RMIN  
=
=1.8KΩ  
Must be  
steady  
Will be  
steady  
100  
80  
tR  
RMAX  
MAX.  
=
May change  
from Low to  
High  
Will change  
from Low to  
High  
CBUS  
60  
40  
20  
0
RESISTANCE  
May change  
from High to  
Low  
Will change  
from High to  
Low  
MIN.  
RESISTANCE  
Don’t Care:  
Changes  
Allowed  
Changing:  
State Not  
Known  
0
20 40 60 80 100 120  
BUS CAPACITANCE (pF)  
N/A  
Center Line  
is High  
Impedance  
7020 FRM 16  
11