X24001SI-2.7 参数 Datasheet PDF下载

X24001

Bus Timing

tF

SCL

tSU:STA

SDA IN

tAA

SDA OUT

3830 FHD F09

tHIGH

tLOW

tR

tHD:STA

tHD:DAT

tSU:DAT

tSU:STO

tDH

tBUF

WRITE CYCLE LIMITS

Symbol

t

WR(4)

Parameter

Write Cycle Time

Min.

Max.

5

Units

ms

3830 PGM T09

Write Cycle Timing

SCL

SDA

D0

tWR

START

CONDTION

X24001

ADDRESS

3830 ILL F10.1

Note:

(3) t

PUR

and t

PUW

are the delays required from the time V

CC

is stable until the specified operation can be initiated. These parameters

are periodically sampled and not 100% tested.

(4) The write cycle time is the time from the initiation of a write sequence to the end of the internal erase/program cycle. During the

write cycle, the X24001 bus interface circuits are disabled, SDA is high impedance, and the device does not respond to start

conditions.

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