X20C17
DEVICE OPERATION
The
CE, OE,
and
WE
inputs control the X20C17 opera-
tion. The X20C17 byte-wide NOVRAM uses a
2-line control architecture to eliminate bus contention in
a system environment. The I/O bus will be in a high
impedance state when either
OE
or
CE
is HIGH.
RAM Operations
RAM read and write operations are performed as they
would be with any static RAM. A read operation requires
CE
and
OE
to be LOW. A write operation requires
CE
and
WE
to be LOW. There is no limit to the number of
read or write operations performed to the RAM portion
of the X20C17.
Memory Transfer Operations
There are two memory transfer operations: a recall
operation whereby the data stored in the E
2
PROM array
is transferred to the RAM array; and a store operation
which causes the entire contents of the RAM array to be
stored in the E
2
PROM array.
Recall operations are performed automatically upon
power-up.
Store operations are performed automatically upon
power-down. The store operation take a maximum of
2.5ms.
Write Protection
The X20C17 supports two methods of protecting the
nonvolatile data.
—If after power-up no RAM write operations have
occured, no AUTOSTORE operation can be initiated.
—V
CC
Sense – All functions are inhibited when V
CC
is
≤
3V typical.
WAVEFORM
INPUTS
Must be
steady
May change
from LOW
to HIGH
May change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
OUTPUTS
Will be
steady
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Changing:
State Not
Known
Center Line
is High
Impedance
SYMBOL TABLE
The following symbol table provides a key to under-
standing the conventions used in the device timing
diagrams. The diagrams should be used in conjunction
with the device timing specifications to determine actual
device operation and performance, as well as device
suitability for user’s application.
3
XICOR [ XICOR INC. ]
