X20C16
PIN NAMES
Symbol
A
0
–A
10
I/O
0
–I/O
7
WE
CE
OE
NE
AS
V
CC
V
SS
NC
AUTOSTORE Output (AS)
Description
Address inputs
Data input/output
Write enable
Chip enable
Output enable
Nonvolatile enable
AUTOSTORE output
+5V
Ground
No connect
AS is an open drain output which, when asserted indi-
cates V
CC
has fallen below the AUTOSTORE threshold
(V
ASTH
). AS may be wire-ORed with multiple open drain
outputs and used as an interrupt input to a microcontroller.
DEVICE OPERATION
RAM Operations
PIN DESCRIPTIONS
Addresses (A
0
–A
10
)
The Address inputs select an 8-bit memory location
during a read or write operation.
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Output Enable (OE)
The Output Enable input controls the data output buffers
and is used to initiate read and recall operations. Out-
put Enable LOW disables a store operation regardless
of the state of CE, WE, or NE.
Data In/Data Out (I/O
0
–I/O
7
)
Data is written to or read from the X20C16 through the
I/O pins. The I/O pins are placed in the high impedance
state when either CE or OE is HIGH or when NE is LOW.
Write Enable (WE)
The Write Enable input controls the writing of data to
the static RAM.
Nonvolatile Enable (NE)
The Nonvolatile Enable input controls the recall func-
tion to the EEPROM array.
et
e
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/
write operations. When CE is HIGH, power consump-
tion is reduced.
O
bs
P
RAM read and write operations are performed as they
would be with any static RAM. A read operation requires
CE and OE to be LOW with WE and NE HIGH. A write
operation requires CE and WE to be LOW with NE HIGH.
There is no limit to the number of read or write operations
performed to the RAM portion of the X20C16.
Memory Transfer Operations
There are two memory transfer operations: a recall
operation whereby the data stored in the EEPROM
array is transfered to the RAM array; and a store oper-
ation which causes the entire contents of the RAM
array to be stored in the EEPROM array.
Recall operations are performed automaticaly upon
power-up and under host system control when NE, OE
and CE are LOW and WE is HIGH. The recall opera-
tion takes a maximum of 5µs.
SDP (Software Data Protection)
There are two methods on initiating a store operation.
The first is the software store command. This com-
mand takes the place of the hardware store employed
on the X20C04. This command is issued by entering
into the special command mode: NE, CE, and WE
strobe LOW while at the same time a specific address
and data combination is sent to the device. This is a
three step operation: the first address/data combina-
tion is 555[H]/AA[H]; the second combination is
2AA[H]/55[H]; and the final command conbination is
555[H]/33[H]. This sequence of pseudo write opera-
tions will immediately initiate a store operation. Refer
to the software command timing diagrams for details
on set and hold times for the various signals.
ro
du
The CE, OE, WE and NE inputs control the X20C16
operation. The X20C16 byte-wide NOVRAM uses a 2-line
control architecture to eliminate bus contention in a sys-
tem environment. The I/O bus will be in a high impedance
state when either OE or CE is HIGH, or when NE is LOW.
REV 1.0 6/21/00
www.xicor.com
Characteristics subject to change without notice.
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XICOR [ XICOR INC. ]
