Preliminary Information
X1288
frequency. For example, a >20ppm frequency deviation
translates into an accuracy of >1 minute per month.
these parameters are available from the crystal
manufacturer. Xicor’s RTC family provides on-chip crystal
compensation networks to adjust load-capacitance to
tune oscillator frequency from +116 ppm to –37 ppm
when using a 12.5 pF load crystal. For more detail
information see the Application section.
Each register is read and written through buffers. The
non-volatile portion (or the counter portion of the RTC) is
updated only if RWEL is set and only after a valid write
operation and stop bit. A sequential read or page write
operation provides access to the contents of only one
section of the CCR per operation. Access to another sec-
tion requires a new operation. Continued reads or writes,
once reaching the end of a section, will wrap around to
the start of the section. A read or write can begin at any
address in the CCR.
CLOCK/CONTROL REGISTERS (CCR)
The Control/Clock Registers are located in an area
separate from the EEPROM array and are only
accessible following a slave byte of “1101111x” and
reads or writes to addresses [0000h:003Fh]. The
clock/control memory map has memory addresses
from 0000h to 003Fh. The defined addresses are
described in the Table 1. Writing to and reading from
the undefined addresses are not recommended.
It is not necessary to set the RWEL bit prior to writing
the status register. Section 5 supports a single byte
read or write only. Continued reads or writes from this
section terminates the operation.
The state of the CCR can be read by performing a ran-
dom read at any address in the CCR at any time. This
returns the contents of that register location. Addi-
tional registers are read by performing a sequential
read. The read instruction latches all Clock registers
into a buffer, so an update of the clock does not
change the time being read. A sequential read of the
CCR will not result in the output of data from the mem-
ory array. At the end of a read, the master supplies a
stop condition to end the operation and free the bus.
After a read of the CCR, the address remains at the
previous address +1 so the user can execute a current
address read of the CCR and continue reading the
next Register.
CCR Access
The contents of the CCR can be modified by perform-
ing a byte or a page write operation directly to any
address in the CCR. Prior to writing to the CCR
(except the status register), however, the WEL and
RWEL bits must be set using a two step process (See
section “Writing to the Clock/Control Registers.”)
The CCR is divided into 5 sections.These are:
1. Alarm 0 (8 bytes; non-volatile)
2. Alarm 1 (8 bytes; non-volatile)
3. Control (4 bytes; non-volatile)
4. Real Time Clock (8 bytes; volatile)
5. Status (1 byte; volatile)
Table 1. Clock/Control Memory Map
Bit
Reg
3
Addr.
003F
0037
0036
0035
0034
0033
0032
0031
0030
0013
0012
0011
0010
Type
Name
SR
7
BAT
SS23
0
6
AL1
SS22
0
5
AL0
SS21
0
4
0
±
0
2
1
(optional) Range
Status
RWEL
SS12
DY2
Y12
WEL
SS11
DY1
Y11
RTCF
01h
xxh
xxh
xxh
xxh
xxh
xxh
xxh
xxh
00h
00h
00h
18h
RTC
(SRAM)
SSEC
DW
YR
SS20
0
SS13
0
SS10
DY0
Y10
0-99
0-6
Y23
0
Y22
0
Y21
0
Y20
G20
D20
H20
M20
S20
0
Y13
G13
D13
H13
M13
S13
0
0-99
1-12
1-31
0-23
0-59
0-59
MO
DT
G12
G11
D11
G10
D10
0
0
D21
H21
M21
S21
0
D12
HR
MIL
0
0
H12
H11
H10
MN
M22
S22
0
M12
S12
M11
S11
M10
S10
SC
0
Control
(EEPROM)
DTR
ATR
INT
BL
0
DTR2
ATR2
DTR1
ATR1
DTR0
ATR0
0
0
ATR5
AL0E
BP0
ATR4
FO1
WD1
ATR3
FO0
WD0
IM
BP2
AL1E
BP1
Read Only Read Only Read Only
Read Only Read Only Read Only
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REV 1.1.30 3/24/04
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