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X1288V14I-2.7 参数 Datasheet PDF下载

X1288V14I-2.7图片预览
型号: X1288V14I-2.7
PDF下载: 下载PDF文件 查看货源
内容描述: 2线RTC实时时钟/日历/ CPU监控器, EEPROM [2-Wire RTC Real Time Clock/Calendar/CPU Supervisor with EEPROM]
分类和应用: 外围集成电路光电二极管监控可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
文件页数/大小: 31 页 / 559 K
品牌: XICOR [ XICOR INC. ]
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Preliminary Information  
X1288  
array the slave byte must be 1010111x in both  
instances. Similarly, for a random read of the Clock/  
Control Registers, the slave byte must be 1101111x in  
both places.  
Page Write  
The X1288 has a page write operation. It is initiated in  
the same manner as the byte write operation; but  
instead of terminating the write cycle after the first data  
byte is transferred, the master can transmit up to 127  
more bytes to the memory array and up to 7 more  
bytes to the clock/control registers. (Note: Prior to writ-  
ing to the CCR, the master must write a 02h, then 06h  
to the status register in two preceding operations to  
enable the write operation. See “Writing to the Clock/  
Control Registers.”  
Write Operations  
Byte Write  
For a write operation, the device requires the Slave  
Address Byte and the Word Address Bytes. This gives  
the master access to any one of the words in the array  
or CCR. (Note: Prior to writing to the CCR, the master  
must write a 02h, then 06h to the status register in two  
preceding operations to enable the write operation.  
See “Writing to the Clock/Control Registers.Upon  
receipt of each address byte, the X1288 responds with  
an acknowledge. After receiving both address bytes  
the X1288 awaits the eight bits of data. After receiving  
the 8 data bits, the X1288 again responds with an  
acknowledge. The master then terminates the transfer  
by generating a stop condition. The X1288 then begins  
an internal write cycle of the data to the nonvolatile  
memory. During the internal write cycle, the device  
inputs are disabled, so the device will not respond to  
any requests from the master. The SDA output is at high  
impedance. See Figure 12.  
After the receipt of each byte, the X1288 responds with  
an acknowledge, and the address is internally incre-  
mented by one. When the counter reaches the end of  
the page, it “rolls over” and goes back to the first  
address on the same page. This means that the mas-  
ter can write 128 bytes to a memory array page or 8  
bytes to a CCR section starting at any location on that  
page. For example, if the master begins writing at loca-  
tion 105 of the memory and loads 30 bytes, then the  
first 23 bytes are written to addresses 105 through  
127, and the last 7 bytes are written to columns 0  
through 6. Afterwards, the address counter would point  
to location 7 on the page that was just written. If the  
master supplies more than the maximum bytes in a  
page, then the previously loaded data is over written by  
the new data, one byte at a time. Refer to Figure 13.  
A write to a protected block of memory is ignored, but  
will still receive an acknowledge. At the end of the write  
command, the X1288 will not initiate an internal write  
cycle, and will continue to ACK commands.  
The master terminates the Data Byte loading by issu-  
ing a stop condition, which causes the X1288 to begin  
the nonvolatile write cycle. As with the byte write oper-  
Figure 12. Byte Write Sequence  
S
t
a
r
Signals from  
the Master  
S
t
o
p
Slave  
Address  
Word  
Address 1  
Word  
Address 0  
t
Data  
SDA Bus  
1
1 1 1 0  
0
A
C
K
A
C
K
A
C
K
A
C
K
Signals From  
The Slave  
Figure 1±. Writing 30 bytes to a 128-byte memory page starting at address 105.  
7 Bytes  
23 Bytes  
Address Pointer  
Ends Here  
Addr = 7  
Address  
105  
Address  
= 6  
Address  
127  
21 of 31  
REV 1.1.30 3/24/04  
www.xicor.com  
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