Preliminary Information
X1288
Table 6. Digital Trimming Registers
DTR Register
– Write one to 8 bytes to the Clock/Control Registers
with the desired clock, alarm, or control data. This
sequence starts with a start bit, requires a slave byte
of “11011110” and an address within the CCR and is
terminated by a stop bit. A write to the CCR changes
EEPROM values so these initiate a nonvolatile write
cycle and will take up to 10ms to complete. Writes to
undefined areas have no effect. The RWEL bit is
reset by the completion of a nonvolatile write cycle,
so the sequence must be repeated to again initiate
another change to the CCR contents. If the
Estimated frequency
DTR2
DTR1
DTR3
PPM
0
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
+10
+20
+30
0
-10
-20
-30
sequence is not completed for any reason (by send-
ing an incorrect number of bits or sending a start
instead of a stop, for example) the RWEL bit is not
reset and the device remains in an active mode.
Analog Trimming Register (ATR) (Non-volatile)
Six analog trimming Bits from ATR5 to ATR3 are pro-
vided to adjust the on-chip loading capacitance range.
The on-chip load capacitance ranges from 3.25pF to
18.75pF. Each bit has a different weight for capacitance
adjustment. Using a Citizen CFS-206 crystal with differ-
ent ATR bit combinations provides an estimated ppm
range from +116ppm to -37ppm to the nominal frequency
compensation. The combination of digital and analog
trimming can give up to +146ppm adjustment.
– Writing all zeros to the status register resets both the
WEL and RWEL bits.
– A read operation occurring between any of the previ-
ous operations will not interrupt the register write
operation.
POWER ON RESET
Application of power to the X1288 activates a Power
On Reset Circuit that pulls the RESET pin active. This
signal provides several benefits.
The on-chip capacitance can be calculated as follows:
C
= [(ATR value, decimal) x 0.25pF] + 11.0pF
ATR
– It prevents the system microprocessor from starting
to operate with insufficient voltage.
Note that the ATR values are in two’s complement, with
ATR(000000) = 11.0pF, so the entire range runs from
3.25pF to 18.75pF in 0.25pF steps.
– It prevents the processor from operating prior to sta-
bilization of the oscillator.
The values calculated above are typical, and total load
capacitance seen by the crystal will include approxi-
mately 2pF of package and board capacitance in addi-
tion to the ATR value.
– It allows time for an FPGA to download its configura-
tion prior to initialization of the circuit.
– It prevents communication to the EEPROM, greatly
reducing the likelihood of data corruption on power up.
See Application section and Xicor’s Application Note
AN154 for more information.
When V
exceeds the device V
threshold value
CC
TRIP
for typically, 250ms the circuit releases RESET, allow-
ing the system to begin operation. Recommended V
slew rate is between 0.2V/ms and 50V/ms.
CC
WRITING TO THE CLOCK/CONTROL REGISTERS
Changing any of the nonvolatile bits of the clock/
control register requires the following steps:
WATCHDOG TIMER OPERATION
– Write a 02h to the Status Register to set the Write
Enable Latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation pre-
ceeded by a start and ended with a stop).
The watchdog timer is selectable. By writing a value to
WD1 and WD0, the watchdog timer can be set to 3 dif-
ferent time out periods or off. When the Watchdog
timer is set to off, the watchdog circuit is configured for
low power operation.
– Write a 06h to the Status Register to set both the
Register Write Enable Latch (RWEL) and the WEL
bit. This is also a volatile cycle. The zeros in the data
byte are required. (Operation preceeded by a start
and ended with a stop).
16 of 31
REV 1.1.30 3/24/04
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