Preliminary Information
X1288
DESCRIPTION
PIN DESCRIPTIONS
The X1288 device is a Real Time Clock with clock/
calendar, two polled alarms with integrated 32kx8
EEPROM, oscillator compensation, CPU Supervisor
(POR/LVS and WDT) and battery backup switch.
X1288
14-pin TSSOP
16-pin SOIC
X1
V
V
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
BACK
X1
X2
CC
1
2
14
13
12
11
10
9
X2
V
BACK
NC
NC
PHZ/IRQ
NC
PHZ/IRQ
NC
NC
NC
3
4
5
6
The oscillator uses an external, low-cost 32.768kHz
crystal. All compensation and trim components are
integrated on the chip. This eliminates several external
discrete components and a trim capacitor, saving
board area and component cost.
NC
NC
NC
NC
NC
NC
RESET
SCL
RESET
SCL
SDA
V
SDA
SS
7
8
V
SS
NC = No internal connection
The Real-Time Clock keeps track of time with separate
registers for Hours, Minutes, Seconds and 1/100 of a
second. The Calendar has separate registers for Date,
Month, Year and Day-of-week. The calendar is correct
through 2099, with automatic leap year correction.
Serial Clock (SCL)
The SCL input is used to clock all data into and out of
the device. The input buffer on this pin is always active
(not gated).
The powerful Dual Alarms can be set to any Clock/
Calendar value for a match. For instance, every
minute, every Tuesday, or 5:23 AM on March 21. The
alarms can be polled in the Status Register or provide
a hardware interrupt (IRQ Pin). There is a repeat
mode for the alarms allowing a periodic interrupt.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into and
out of the device. It has an open drain output and may
be wire ORed with other open drain or open collector
outputs.The input buffer is always active (not gated).
The PHZ/IRQ pin may be software selected to provide
a frequency output of 1 Hz, 100 Hz, or 32,768 Hz.
An open drain output requires the use of a pull-up
resistor. The output circuitry controls the fall time of the
output signal with the use of a slope controlled pull-
down. The circuit is designed for 400kHz 2-wire inter-
face speed.
The X1288 device integrates CPU Supervisor func-
tions and a Battery Switch. There is a Power-On Reset
(RESET output) with typically 250 ms delay from power
on. It will also assert RESET when Vcc goes below the
V
BACK
specified threshold. The V
threshold is user repro-
trip
This input provides a backup supply voltage to the
grammable. There is a WatchDog Timer (WDT) with 3
selectable time-out periods (0.25s, 0.75s, 1.75s) and a
disabled setting. The watchdog activates the RESET
pin when it expires.
device. V
event the V
supplies power to the device in the
supply fails. This pin can be connected
BACK
CC
to a battery, a Supercap or tied to ground if not used.
The device offers a backup power input pin. This
RESET Output – RESET
V
pin allows the device to be backed up by battery
BACK
This is a reset signal output. This signal notifies a host
processor that the watchdog time period has expired or
that the voltage has dropped below a fixed V
old. It is an open drain active LOW output. Recom-
mended value for the pullup resistor is 5K Ohms. If
unused, tie to ground.
or SuperCap. The entire X1288 device is fully
operational from 2.7 to 5.5 volts and the clock/calendar
portion of the X1288 device remains fully operational
down to 1.8 volts (Standby Mode).
thresh-
TRIP
The X1288 device provides 256K bits of EEPROM with 8
modes of BlockLock™ control. The BlockLock allows a
safe, secure memory for critical user and configuration
data, while allowing a large user storage area.
Programmable Frequency/Interrupt Output – PHZ/IRQ
This is either an output from the internal oscillator or an
interrupt signal output. It is a CMOS output.
10 of 31
REV 1.1.30 3/24/04
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XICOR [ XICOR INC. ]
