X1228
Figure 13. Slave Address, Word Address, and Data Bytes (64 Byte pages)
Device Identifier
Array
CCR
1
1
0
1
1
0
0
1
Slave Address Byte
Byte 0
1
0
1
1
0
R/W
A8
Word Address 1
Byte 1
0
0
0
0
0
Word Address 0
Byte 2
A7
D7
A6
D6
A5
D5
A4
D4
A3
D3
A2
D2
A1
D1
A0
D0
Data Byte
Byte 3
Write Operations
Byte Write
the X1228 awaits the eight bits of data. After receiving
the 8 data bits, the X1228 again responds with an
acknowledge. The master then terminates the transfer
by generating a stop condition. The X1228 then begins
an internal write cycle of the data to the nonvolatile
memory. During the internal write cycle, the device
inputs are disabled, so the device will not respond to
any requests from the master. The SDA output is at high
impedance. See Figure 11.
For a write operation, the device requires the Slave
Address Byte and the Word Address Bytes. This gives
the master access to any one of the words in the array
or CCR. (Note: Prior to writing to the CCR, the master
must write a 02h, then 06h to the status register in two
preceding operations to enable the write operation.
See “Writing to the Clock/Control Registers.” Upon
receipt of each address byte, the X1228 responds with
an acknowledge. After receiving both address bytes
Figure 11. Byte Write Sequence
S
t
a
r
Signals from
the Master
S
t
o
p
Slave
Address
Word
Address 1
Word
Address 0
t
Data
SDA Bus
0 0 0 0 0 0 0
1
1 1 1 0
A
C
K
A
C
K
A
C
K
A
C
K
Signals From
The Slave
Figure 12. Writing 30 bytes to a 64-byte memory page starting at address 40.
7 Bytes
23 Bytes
Address Pointer
Ends Here
Addr = 7
Address
Address
= 6
Address
40
63
Characteristics subject to change without notice. 20 of 31
REV 1.3 3/24/04
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