ISL29038
ISL29038 Configuration and
Control
I
2
C Interface
ISL29038 configuration and control is performed using the I
2
C or
SMBus. The ISL29038’s I
2
C interface slave address is internally
hard wired as 8’b1000100x, where x denotes the R/W bit.
Every I
2
C transaction begins with the master asserting a start
condition (SDA falling while SCL remains high). The first
transmitted byte is initiated by the master and includes 7
address bits and a R/W bit. The slave is responsible for pulling
SDA low during the ACK time after every transmitted byte.
Figure 5 shows a sample one-byte read. The I
2
C bus master
always drives the SCL (clock) line, while either the master or the
slave can drive the SDA (data) line.
Each I
2
C transaction ends with the master asserting a stop
condition (SDA rising while SCL remains high). For more
information about the I
2
C standard, consult the Philips
™
I
2
C
specification documents.
Timing specifications are included in “I
Figure 4.
The I
2
C interface on the ISL29038 supports single and multiple
byte read and write transfers using the random-read/write
protocol. The ISL29038 does not support I
2
C ‘Repeat Start’
protocol.
Note that in most system implementations, the ISL29038 is
connected to a single I
2
C master with one or more slave devices,
consequently, absence of ‘Repeat Start’ function does not
adversely affect I
2
C bus system performance.
I
2
C DATA
I
2
C SDA
MASTER
START
DEVICE ADDRESS
W A
REGISTER ADDRESS
STOP START
DEVICE ADDRESS
A
DATA BYTE0
A6 A5 A4 A3 A2 A1 A0 W A R7 R6 R5 R4 R3 R2 R1 R0 A
A6 A5 A4 A3 A2 A1 A0 W
A
SDA DRIVEN BY ISL29038
I
2
C SDA
SLAVE
(ISL29038)
SDA DRIVEN BY MASTER
A
SDA DRIVEN BY MASTER
A
SDA DRIVEN BY MASTER
A D7 D6 D5 D4 D3 D2 D1 D0
I
2
C CLK
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
FIGURE 5. I
2
C DRIVER TIMING DIAGRAM FOR MASTER AND SLAVE CONNECTED TO COMMON BUS
6
FN7851.0
October 12, 2012
XICOR [ XICOR INC. ]
