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5962-9086903MXA 参数 Datasheet PDF下载

5962-9086903MXA图片预览
型号: 5962-9086903MXA
PDF下载: 下载PDF文件 查看货源
内容描述: [EEPROM, 64KX8, 200ns, Parallel, CMOS, CDIP32, HERMETIC SEALED, CERDIP-32]
分类和应用: 可编程只读存储器电动程控只读存储器电可擦编程只读存储器内存集成电路
文件页数/大小: 24 页 / 114 K
品牌: XICOR [ XICOR INC. ]
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X28C512/X28C513  
HARDWARE DATA PROTECTION  
The X28C512/513 can be automatically protected dur-  
ing power-up and power-down without the need for  
external circuits by employing the software data protec-  
tion feature. The internal software data protection circuit  
is enabled after the first write operation utilizing the  
software algorithm. This circuit is nonvolatile and will  
remain set for the life of the device unless the reset  
command is issued.  
The X28C512/513 provides three hardware features  
that protect nonvolatile data from inadvertent writes.  
• Noise Protection—A WE pulse typically less than  
10ns will not initiate a write cycle.  
• Default V Sense—All write functions are inhibited  
CC  
when V is 3.6V.  
CC  
• Write Inhibit—Holding either OE LOW, WE HIGH,  
or CE HIGH will prevent an inadvertent write cycle  
during power-up and power-down, maintaining data  
integrity. Write cycle timing specifications must be  
observed concurrently.  
Once the software protection is enabled, the X28C512/  
513 is also protected from inadvertent and accidental  
writes in the powered-up state. That is, the software  
algorithm must be issued prior to writing additional data  
to the device. Note: The data in the three-byte enable  
sequence is not written to the memory array.  
SOFTWARE DATA PROTECTION  
The X28C512/513 offers a software controlled data  
protection feature. The X28C512/513 is shipped from  
Xicor with the software data protection NOT ENABLED;  
thatis,thedevicewillbeinthestandardoperatingmode.  
In this mode data should be protected during power-up/  
-down operations through the use of external circuits.  
The host would then have open read and write access  
SOFTWARE ALGORITHM  
Selecting the software data protection mode requires  
the host system to precede data write operations by a  
series of three write operations to three specific ad-  
dresses. Refer to Figure 4a and 4b for the sequence.  
The three byte sequence opens the page write window  
enabling the host to write from one to one hundred  
twenty-eightbytesofdata.Oncethepageloadcyclehas  
been completed, the device will automatically be re-  
turned to the data protected state.  
of the device once V was stable.  
CC  
6
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