X28C512/X28C513
CE Controlled Write Cycle
t
WC
ADDRESS
t
t
AS
AH
t
CW
CE
t
WPH
t
OES
OE
t
OEH
t
CS
t
CH
WE
t
DV
DATA IN
DATA VALID
t
t
DS
HIGH Z
DH
DATA OUT
3856 FHD F18
Page Write Cycle
OE(5)
CE
t
t
BLC
WP
WE
t
WPH
*ADDRESS(6)
I/O
LAST BYTE
BYTE n+2
BYTE 0
BYTE 1
BYTE 2
BYTE n
BYTE n+1
t
WC
*For each successive write within the page write operation, A –A should be the same or
15
7
writes to an unknown address could occur.
3856 FHD F19.1
Notes: (5) Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE HIGH
to fetch data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively performing
a polling operation.
(6) The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform
to either the CE or WE controlled write cycle timing.
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