TABLE I. Electrical performance characteristics - Continued.
Test
│
│Symbol
│
│
│
│
│
│
│t
WHEL
│t
EHEL
5/
│
│
│t
ELWL
5/
│
│
5/
│t
OVHWL
│
│
│
│
Conditions
│
-55°C
≤
T
C
≤+125°C
│
V
SS
= 0 V,
│
4.5 V
≤
V
CC
≤
5.5 V
│unless
otherwise specified 1/
│
│
│See
figure 5 or 6
│
as applicable
│
│
│See
figure 8
│
│
│
│
│
│
│Group
A
│subgroups
│
│
│
│
│
│
9,10,11
│
│
│
│
9,10,11
│
│
│
9,10,11
│
│
│
9,10,11
│
│
│
9,10,11
│
│
│
9,10,11
│
│
│
9,10,11
│
│
│
9,10,11
│
│
│
Device
│
types
│
│
│
│
│
│
All
│
│
│
│
All
│
│
│
All
│
│
│
All
│
│
│
All
│
│
│
All
│
│
│
All
│
│
│
All
│
│
│
Limits
│
│
│
│
Min
│
Max
│
│
│
│
│
│
│
│
650
│
│
│
│
│
│
│
5
│
│
│
5
│
│
│
5
│
│
│
5
│
│
│
12
│
│
│
│
│
│
10
│
│
│
│
│
│
│
│
│
│
│
│
│
│
13
│
│
│210
│
│
│
│
│
│
Unit
│
│
│
│
│
│
│
µs
│
│
│
│
µs
│
│
│
µs
│
│
│
µs
│
│
│
µs
│
│
│
V
│
│
│
ms
│
│
│
ms
│
Last byte loaded to
data polling
CE setup time
Output set-up time
CE hold time
│t
WHEH
5/
│
│
│
│
│
5/
│t
WHOH
│
│
│V
H
5/
│
│
5/
│t
WLWH2
│
│
│
│
│
│
│
│
│
│
│
OE hold time
High voltage
Chip erase
WE
pulse width for
chip erase
│t
WLWH1
5/
│
│
│
1/
2/
3/
4/
5/
DC and read mode.
Connect all address inputs and OE to V
IH
and measure I
OLZ
and I
OHZ
with the output under test connected to V
OUT
.
All pins not being tested are to be open.
Tested initially and after any design or process changes that affect that parameter, and therefore shall be guaranteed to the
limits specified in table I.
Tested by application of specified timing signals and conditions, including:
Equivalent ac test conditions:
Devices: All.
Output load: 1 TTL gate and C
L
= 100 pF (minimum) or equivalent circuit.
Input rise and fall times
≤
10 ns.
Input pulse levels: 0.4 V and 2.4 V.
Timing measurements reference levels:
Inputs: 1 V and 2 V.
Outputs: 0.8 V and 2 V.
6/
During a page write operation the cycle time defined by t
WLWH
and t
WHWL2
shall not be less than 1 µs.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
A
REVISION LEVEL
5962-88525
SHEET
D
8
XICOR [ XICOR INC. ]
