TABLE I. Electrical performance characteristics - Continued.
│
│
│
│
│
│
│
│
│
│
Test
│Symbol
│
│
Conditions 1/ 2/
│ Group A │ Device
│subgroups│ type
│
│
│
│
Limits
│ Unit
│
│
│ -55°C < TC <+125°C
│VSS = 0 V 4.5 V < VCC < 5.5 V
│ unless otherwise specified
│
│
│
│
│
│
│
│
│ Min
│
│
│ Max
│
│
│
│
│
│
│
Chip erase time 6/
High voltage 6/
│tWLWH2
│
│See figure 8, configuration
│A or B
│
│
│
│ 9,10,11 │01-05,
│150
│
│
│
│
│
│
│
│ 13
│
│
│ ns
│
│
│ ms
│
│ V
│
│
│
│
│23-27
│
│06-22,28 │ 10
│
│
6/
│
│
│VH
│
│
│
│
│ 9,10,11 │ All
│ 12
│
│
│
│
│
│
│
│
│
│
Time to device
busy
│tEHRL
│tWHRL
│
│See figures 6 and 7
│ 9,10,11 │13-17,28 │
│ 50
│100
│
│ ns
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│23-27
│
│
│
│
│
│
│
│
│
│
Write cycle time
RDY/BUSY
│tELRH
│tWLRH
│
│ 9,10,11 │13-17,28 │
│ 1
│ 10
│
│
│ 1
│
│ ms
│
│
│
│23-27
│
│
│
│
│
│
│
│
│
Maximum time to 6/
valid data after
WE/CE low
│tWLDV
│tELDV
│
│ 9,10,11 │13-22,28 │
│ µs
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
1/ DC and read mode.
2/ Equivalent ac test conditions:
Device types: 01 through 09 and 13 through 28.
Output load: 1 TTL gate and C1 = 100 pF,
Input rise and fall times < 10 ns.
Input pulse levels: 0.4 V and 2.4 V.
Timing measurements reference levels:
Inputs 1 V and 2 V.
Device types: 10 through 12.
Output load: 1 TTL gate and C1 = 30 pF.
Input rise and fall times < 5 ns.
Input pulse levels: 0.4 V and 2.4 V.
Inputs 1 V and 2 V.
Outputs 0.8 V and 2 V.
Outputs 0.8 V and 2 V.
3/ Connect all address inputs and OE to VIH and measure IOLZ and IOHZ with the output under test connected to VOUT
4/ All pins not being tested are to be open.
.
5/ Tested initially and after any design or process changes that affect that parameter, and therefore guaranteed to the limits
specified in table I.
6/ Tested by application of specified timing signals and conditions, see footnote 2/.
SIZE
STANDARD
5962-87514
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
E
SHEET
11
DSCC FORM 2234
APR 97
XICOR [ XICOR INC. ]
