WPMDH1100601 / 171010601
MagI3C Power Module
VDRM – Variable Step Down Regulator Module
Selection by load step requirements
The output voltage is also affected by load transients (see picture below). The constant on-time control scheme generally
provides faster response than the other control loops.
When the output current transitions from a low to a high value, the voltage at the output capacitor (VOUT) drops due to two
contributing factors. One is caused by the voltage drop across the ESR (VESR) and depends on the slope of the rising edge
of the current step (trise). For low ESR values and small load currents, this is often negligible. It can be calculated as follows:
VESR=ESR∙∆IOUT
(13)
where ∆IOUT is the load step, as shown in the picture below (simplified: no voltage ripple is shown).
IOUT
∆IOUT
trise
0
t
VOUT
VESR
∆VOUT
Vdischarge
0
t
td
treg
we-online.com
Würth Elektronik eiSos GmbH & Co. KG – Data Sheet Rev. 1.0
© September 2017
23/54
WURTH [ WURTH ELEKTRONIK GMBH & CO. KG, GERMANY. ]
