WM8985
Pre-Production
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0001
0010
45.4us
90.8us
363.2us 2.62ms
726.4us 5.26ms
… (time doubles with every step)
1010 23.2ms 186ms 1.348s
Table 20 ALC Control Registers
When the ALC is disabled, the input PGA remains at the last controlled value of the ALC. An input
gain update must be made by writing to the INPPGAVOLL/R register bits.
NORMAL MODE
In normal mode, the ALC will attempt to maintain a constant signal level by increasing or decreasing
the gain of the PGA. The following diagram shows an example of this.
Figure 21 ALC Normal Mode Operation
PP, Rev 3.4, October 2006
44
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