Pre-Production
WM8985
The polarity of the output signal can also be changed under software control using the
ADCLPOL/ADCRPOL register bit. The oversampling rate of the ADC can be adjusted using the
ADCOSR128 register bit. With ADCOSR=0 the oversample rate is 64x which gives lowest power
operation and when ADCOSR=1 the oversample rate is 128x which gives best performance.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R14 (0Eh)
ADC Control
0
ADCLPOL
0
ADC left channel polarity adjust:
0 = normal
1 = inverted
1
3
ADCRPOL
0
0
ADC right channel polarity adjust:
0 = normal
1 = inverted
ADCOSR128
ADC oversample rate select:
0 = 64x (lower power)
1 = 128x (best performance)
Table 14 ADC Control
SELECTABLE HIGH PASS FILTER
A selectable high pass filter is provided and enabled as default. To disable this filter set HPFEN=0.
The filter has two modes controlled by HPFAPP. In Audio Mode (HPFAPP=0) the filter is first order,
with a cut-off frequency of 3.7Hz. In Application Mode (HPFAPP=1) the filter is second order, with a
cut-off frequency selectable via the HPFCUT register. The cut-off frequencies when HPFAPP=1 are
shown in Table 16.
REGISTER
ADDRESS
BIT
6:4
LABEL
DEFAULT
DESCRIPTION
R14 (0Eh)
HPFCUT
000
Application mode cut-off frequency
See Table 16 for details.
ADC Control
7
HPFAPP
HPFEN
0
1
Select audio mode or application mode
0 = Audio mode (1st order, fc = ~3.7Hz)
1 = Application mode (2nd order, fc =
HPFCUT)
8
High Pass Filter Enable
0 = disabled
1 = enabled
Table 15 ADC Enable Control
HPFCUT
[2:0]
SR=101/100
SR=011/010
fs (kHz)
22.05
SR=001/000
44.1
8
11.025
12
16
24
32
48
000
001
010
011
100
101
110
111
82
113
141
180
225
281
360
450
563
122
153
156
245
306
392
490
612
82
113
141
180
225
281
360
450
563
122
153
156
245
306
392
490
612
82
113
141
180
225
281
360
450
563
122
153
156
245
306
392
490
612
102
131
163
204
261
327
408
102
131
163
204
261
327
408
102
131
163
204
261
327
408
Table 16 High Pass Filter Cut-off Frequencies (HPFAPP=1)
Note that the High Pass filter values (when HPFAPP=1) are calculated on the assumption that the
SR register bits are set correctly for the actual sample rate as shown in Table 16. Sampling rate
(SR) is enabled by register bits R7[1:3].
PP, Rev 3.4, October 2006
39
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
