Pre-Production
WM8959
Test Conditions
DCVDD = 1.8V, DBVDD = 3.3V, AVDD = HPVDD = 3.3V, SPKVDD = 5V, TA = +25oC, 1kHz signal, fs = 48kHz,
PGA gain = 0dB, 24-bit audio data unless otherwise stated.
PARAMETER
TEST CONDITIONS
MIN
-3%
-5%
-5%
TYP
MAX
+3%
+5%
+5%
3
UNIT
Analogue Reference Levels
H1
VMID Midrail Reference Voltage
AVDD/2
V
V
V
Microphone Bias
H2
Bias Voltage
3mA load current
M1BSEL=0 / M2BSEL=0
3mA load current
0.9×AVDD
0.65×AVDD
M1BSEL=1 / M2BSEL=1
H3
H4
H5
Bias Current Source
Output Noise Density
AVDD PSRR (217Hz)
mA
nV/√Hz
dB
1kHz to 20kHz
100mV pk-pk @217Hz
on AVDD
100
45
Digital Input / Output
H6
H7
Input HIGH Level
Input LOW Level
0.7×DBVDD
V
V
0.3×DBVDD
Note that digital input pins should not be left unconnected / floating.
Internal pull-up/pull-down resistors may be enabled on GPIO1, GPIO3, GPIO4 and GPIO5 if required.
H8
Output HIGH Level
Output LOW Level
Input capacitance
Input leakage
I
OL=1mA
0.9×DBVDD
V
V
H9
IOH=-1mA
0.1×DBVDD
H10
H11
PLL
H12
10
pF
uA
-0.9
0.9
Input Frequency
Lock time
PRESCALE = 0b
PRESCALE = 1b
10
20
17
34
MHz
MHz
us
H13
200
GPIO
H14
Clock output duty cycle
(Integer OPCLKDIV)
SYSCLK=MCLK;
OPCLKDIV=0000
SYSCLK=MCLK;
OPCLKDIV=1000
SYSCLK=PLL output;
OPCLKDIV=0000
SYSCLK=PLL output;
OPCLKDIV=1000
SYSCLK=MCLK;
OPCLKDIV=0100
SYSCLK=PLL output;
OPCLKDIV=0100
Input de-bounced
Input de-bounced
TOCLKSEL=1
35
45
45
45
33
33
65
55
55
55
66
66
%
%
%
%
%
%
H15
H16
Clock output duty cycle
(Non-integer OPCLKDIV)
Interrupt response time for accessory /
button detect
221 / fSYSCLK
219 / fSYSCLK
222 / fSYSCLK
220 / fSYSCLK
s
s
Input not de-bounced
0
s
PP, May 2008, Rev 3.1
19
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
