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WM8955L
SIGNAL TIMING REQUIREMENTS
SYSTEM CLOCK TIMING
tMCLKL
MCLK
tMCLKH
tMCLKY
Figure 1 System Clock Timing Requirements
Test Conditions
DBVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
System Clock Timing Information
MCLK System clock pulse width high
MCLK System clock pulse width low
MCLK System clock cycle time
tMCLKL
tMCLKH
tMCLKY
16
16
27
ns
ns
ns
AUDIO INTERFACE TIMING – MASTER MODE
BCLK
(Output)
tDL
DACLRC
(Output)
tDST
tDHT
DACDAT
Figure 2 Digital Audio Data Timing – Master Mode (see Control Interface)
Test Conditions
DBVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
System Clock Timing Information
DACLRC propagation delayfrom BCLK falling edge
DACDAT setup time to BCLK rising edge
DACDAT hold time from BCLK rising edge
tDL
10
ns
ns
ns
tDST
tDHT
10
10
AUDIO INTERFACE TIMING – SLAVE MODE
tBCH
tBCL
BCLK
DACLRC
DACDAT
tBCY
tLRSU
tDS
tLRH
Figure 3 Digital Audio Data Timing – Slave Mode (see Control Interface)
Product Preview Rev 0.4 May2003
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
