Production Data
WM8955BL
REGISTER MAP
REGISTER ADDRESS (BIT 15 – 9)
REMARKS
Reserved
BIT8
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
R0 (00h)
R1 (01h)
R2 (02h)
R3 (03h)
R4 (04h)
R5 (05h)
R6 (06h)
R7 (07h)
R8 (08h)
0000000
0000001
0000010
0000011
0000100
0000101
0000110
0000111
0001000
000000000
000000000
Reserved
LOUT1
LO1VU
RO1VU
LO1ZC
RO1ZC
LOUT1VOL
ROUT1VOL
ROUT1
Reserved
000000000
0
DAC Control
Reserved
0
DAT
0
0
DACMU
DEEMPH
0
000000000
LRP
Audio Interface
Sample Rates
0
0
BCLKINV
BCLK
MS
LRSWAP
WL
FORMAT
MCLK
DIV2
SR
USB
DIV2
R9 (09h)
0001001
0001010
0001011
0001100
Reserved
Left Gain
Right Gain
Bass
000000000
R10 (0Ah)
R11 (0Bh)
LDVU
RDVU
0
LDACVOL (Right DAC Digital Volume)
RDACVOL (Right DAC Digital Volume)
R12
BB
0
BC
TC
0
0
BASS (Bass Intensity)
(0Ch)
R13
0001101
Treble
0
0
0
TRBL (Treble Intensity)
(0Dh)
R14 (0Eh)
R15 (0Fh)
0001110
0001111
Reserved
Reset
000000000
writing 000000000 to this register resets all registers to their default state
000000
R16 –
R22
Reserved
R23 (17h)
R24 (18h)
R25 (19h)
R26 (1Ah)
R27 (1Bh)
0010111
0011000
0011001
0011010
0011011
Additional (1)
Additional (2)
Pwr Mgmt (1)
Pwr Mgmt (2)
Additional (3)
Reserved
TSDEN
VSEL
DMONOMIX
0
0
DACINV
TOEN
DACOSR
DIGENB
0
OUT3SW
VMIDSEL
0
0
ROUT2INV
0
0
0
VREF
LOUT1
VROI
0
ROUT1
0
0
LOUT2
0
0
ROUT2
0
0
MOUT
0
0
OUT3
0
DACL
DACR
0
0
0
R28 –
R33
R34 (22h)
R35 (23h)
R36 (24h)
R37 (25h)
R38 (26h)
R39 (27h)
R40 (28h)
R41 (29h)
R42 (2Ah)
R43 (2Bh)
0100010
0100011
0100100
0100101
0100110
0100111
0101000
0101001
0101010
0101011
Left Mix (1)
Left Mix (2)
Right Mix (1)
Right Mix (2)
Mono Mix (1)
Mono Mix (2)
LOUT2
LD2LO
RD2LO
LD2RO
RD2RO
LD2MO
RD2MO
LO2VU
RO2VU
0
LI2LO
MI2LO
MI2RO
RI2RO
LI2MO
RI2MO
LO2ZC
RO2ZC
MOZC
0
LI2LOVOL
MI2LOVOL
MI2ROVOL
RI2ROVOL
LI2MOVOL
RI2MOVOL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DMEN
0
0
LOUT2VOL
ROUT2VOL
MONOOUTVOL
PLLEN
ROUT2
MONOOUT
Clocking / PLL
MCLKSEL
0
PLLOUT
DIV2
PLL_RB
0
0
0
0
R44
0101100
0101101
PLL Control (1)
PLL Control (2)
N
K [21:18]
(2Ch)
R45
K [17:9]
(2Dh)
R46 (2Eh)
R59 (3Bh)
0101110
0111011
PLL Control (3)
PLL Control (4)
K [8:0]
0
0
KEN
0
0
0
0
0
0
PD Rev 4.1 February 2007
37
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