Production Data
WM8945
CONTROL INTERFACE MODE
2-wire (I2C)
GPIO PIN AVAILABILITY
GPIO1
GPIO1
GPIO1
GPIO2
GPIO3
GPIO3
GPIO3
GPIO4
GPIO4
3-wire (SPI)
4-wire (SPI)
Table 61 GPIO Pin Availability
Note that CIFMODE/GPIO3 pin selects between I2C and SPI Control Interface modes (see “Control
Interface”). To enable GPIO functions on GPIO3, the MODE_GPIO register bit must be set in order to
disconnect this pin from the Control Interface circuit. Setting the MODE_GPIO register bit causes the
Control Interface mode selection to be latched; it will remain latched until a Software Reset or Power
On Reset occurs.
The register fields that control the GPIO pins are described in Table 62.
For each GPIO, the selected function is determined by the GPn_FN field, where n identifies the GPIO
pin (1 to 4). The pin direction, set by GPn_DIR, must be set according to function selected by
GPn_SEL.
When a pin is configured as a GPIO output, its level can be set to logic 0 or logic 1 using the
GPn_LVL field. When a pin is configured as a GPIO input, the logic level can be read from the
respective GPn_LVL bit. The GPIO output is inverted with respect to the GPn_LVL register when the
polarity bit GPn_POL is set; the equivalent is true of GPIO inputs also.
Internal pull-up and pull-down resistors may be enabled using the GPn_PULL fields; this allows
greater flexibility to interface with different signals from other devices.
Each of the GPIO pins is an input to the Interrupt control circuit and can be used to trigger an Interrupt
event. This may be configured as level-triggered or edge-triggered using the GPn_FN registers. Edge
detect raises an interrupt when the GPIO status changes; level detect asserts the interrupt for as long
as the GPIO status is asserted. See “Interrupts”.
An edge-triggered GPIO can be configured to trigger on a single edge or on both edges of the input
signal; this is selected using the GPn_INT_MODE registers. A level-triggered or single-edge-triggered
input may be configured using the GPn_POL registers to respond to a high level/edge (when
GPn_POL = 0) or a low level/edge (when GPn_POL = 1).
The GPIO control fields are defined in Table 60.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R11 (0Bh)
GPIO_MODE
CIFMODE/GPIO3 pin configuration
0 = Pin configured as CIFMODE
1 = Pin configured as GPIO3
0
0
GPIO Config
Note – when this bit is set to 1, it is
latched and cannot be reset until
Power-Off or Software Reset.
R12 (0Ch)
GP1_DIR
GPIO1 Pin Direction
0 = Output
15
1
GPIO1
Control
1 = Input
GP1_PULL [1:0]
GPIO1 pull-up / pull-down Enable
00 = no pull-up or pull-down
01 = pull-down
14:13
00
10 = pull-up
11 = reserved
GP1_INT_
MODE
GPIO1 Interrupt Mode
12
0
0 = GPIO interrupt is rising edge
triggered (if GP1_POL=0) or falling
edge triggered (if GP1_POL =1)
1 = GPIO interrupt is triggered on
rising and falling edges
PD, May 2011, Rev 4.1
91
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
