Production Data
WM8945
OUTPUT SIGNAL PATHS ENABLE
Each analogue output pin can be independently enabled or disabled using the register bits described
in Table 29. The speaker output PGAs and mixers can also be controlled.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R3 (03h)
OUTL_ENA
0
LINEOUTL enable
14
Power
0 = Disabled
management
2
1 = Enabled
SPKR_PGA_ENA
SPKL_PGA_ENA
0
0
0
Speaker Right PGA enable
0 = Disabled
13
12
11
1 = Enabled
Speaker Left PGA enable
0 = Disabled
1 = Enabled
SPKR_SPKVDD_
ENA
SPKOUTR enable
0 = Disabled
1 = Enabled
Note that SPKOUTR is also
controlled by SPKR_OP_ENA.
When powering down SPKOUTR,
the SPKR_SPKVDD_ENA bit
should be reset first.
SPKL_SPKVDD_
ENA
0
SPKOUTL enable
0 = Disabled
10
1 = Enabled
Note that SPKOUTL is also
controlled by SPKL_OP_ENA.
When powering down SPKOUTL,
the SPKL_SPKVDD_ENA bit should
be reset first
SPKR_OP_ENA
0
SPKOUTR enable
0 = Disabled
7
1 = Enabled
Note that SPKOUTR is also
controlled by
SPKR_SPKVDD_ENA. When
powering up SPKOUTR, the
SPKR_OP_ENA bit should be
enabled first.
SPKL_OP_ENA
0
SPKOUTL enable
0 = Disabled
6
1 = Enabled
Note that SPKOUTL is also
controlled by SPKL_SPKVDD_ENA.
When powering up SPKOUTL, the
SPKL_OP_ENA bit should be
enabled first
SPKR_MIX_ENA
SPKL_MIX_ENA
0
0
Right speaker output mixer enable
0 = Disabled
3
2
1 = Enabled
Left speaker output mixer enable
0 = Disabled
1 = Enabled
Table 29 Output Signal Paths Enable
PD, May 2011, Rev 4.1
51
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
