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WM8941GEFLRV 参数 Datasheet PDF下载

WM8941GEFLRV图片预览
型号: WM8941GEFLRV
PDF下载: 下载PDF文件 查看货源
内容描述: 单声道编解码器与扬声器驱动器和视频缓冲器 [Mono CODEC with Speaker Driver and Video Buffer]
分类和应用: 解码器驱动器编解码器
文件页数/大小: 96 页 / 1210 K
品牌: WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
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Pre Production  
WM8941  
TABLE OF CONTENTS  
DESCRIPTION ................................................................................................................1  
FEATURES......................................................................................................................1  
APPLICATIONS ..............................................................................................................1  
BLOCK DIAGRAM ..........................................................................................................2  
PIN CONFIGURATION....................................................................................................5  
ORDERING INFORMATION ...........................................................................................5  
PIN DESCRIPTION .........................................................................................................6  
ABSOLUTE MAXIMUM RATINGS..................................................................................7  
RECOMMENDED OPERATING CONDITIONS ..............................................................7  
ELECTRICAL CHARACTERISTICS ...............................................................................8  
TERMINOLOGY....................................................................................................................10  
AUDIO PATHS OVERVIEW..........................................................................................12  
SIGNAL TIMING REQUIREMENTS..............................................................................14  
SYSTEM CLOCK TIMING .....................................................................................................14  
AUDIO INTERFACE TIMING – MASTER MODE ..................................................................14  
AUDIO INTERFACE TIMING – SLAVE MODE......................................................................15  
CONTROL INTERFACE TIMING – 3-WIRE MODE ..............................................................16  
CONTROL INTERFACE TIMING – 2-WIRE MODE ..............................................................17  
DEVICE DESCRIPTION................................................................................................18  
INTRODUCTION...................................................................................................................18  
INPUT SIGNAL PATH...........................................................................................................19  
ANALOGUE TO DIGITAL CONVERTER (ADC)....................................................................25  
INPUT LIMITER / AUTOMATIC LEVEL CONTROL (ALC) ....................................................30  
OUTPUT SIGNAL PATH .......................................................................................................43  
VOLUME BOOST..................................................................................................................45  
ANALOGUE OUTPUTS.........................................................................................................47  
OUTPUT SWITCH ................................................................................................................50  
VIDEO BUFFER....................................................................................................................53  
DIGITAL AUDIO INTERFACES.............................................................................................58  
AUDIO SAMPLE RATES.......................................................................................................62  
MASTER CLOCK AND PHASE LOCKED LOOP (PLL).........................................................63  
COMPANDING......................................................................................................................66  
GENERAL PURPOSE INPUT/OUTPUT................................................................................68  
CONTROL INTERFACE........................................................................................................68  
3-WIRE SERIAL CONTROL MODE ......................................................................................70  
READBACK IN 3-WIRE MODE .............................................................................................70  
2-WIRE SERIAL CONTROL MODE ......................................................................................71  
RESETTING THE CHIP ........................................................................................................71  
POWER SUPPLIES ..............................................................................................................71  
POWER MANAGEMENT ......................................................................................................74  
POP MINIMISATION .............................................................................................................75  
REGISTER MAP............................................................................................................76  
REGISTER BITS BY ADDRESS ...........................................................................................77  
DIGITAL FILTER CHARACTERISTICS........................................................................89  
TERMINOLOGY....................................................................................................................89  
DAC FILTER RESPONSES...................................................................................................90  
ADC FILTER RESPONSES...................................................................................................90  
HIGHPASS FILTER...............................................................................................................91  
NOTCH FILTERS AND LOW PASS FILTER.........................................................................92  
PP, Rev 3.3, December 2007  
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