WM8941
Pre Production
DESCRIPTION
REGISTER
ADDRESS
BIT
LABEL
VROI
DEFAULT
R49
0
0
VREF (AVDD/2) to analogue output
resistance
0: approx 1kΩ
1: approx 30 kΩ
Table 39 Disabled Outputs to VREF Resistance
A dedicated buffer is available for tying off unused analogue I/O pins as shown in Figure 21. This
buffer can be enabled using the BUFIOEN register bit.
Table 40 summarises the tie-off options for the speaker and mono output pins.
Figure 21 Unused Input/Output Pin Tie-off Buffers
MONOEN/
VROI
OUTPUT CONFIGURATION
SPKN/PEN
0
0
1
0
1
X
1kΩ tieoff to AVDD/2
30kΩ tieoff to AVDD/2
Output enabled (DC level=AVDD/2)
Table 40 Unused Output Pin Tie-off Options
OUTPUT SWITCH
When the device is configured with a 2-wire interface the CSB/GPIO pin can be used as a switch
control input to automatically disable the speaker outputs and enable the mono output. As an
example, when a line is plugged into a jack socket. In this mode, enabled by setting GPIOSEL=001,
pin CSB/GPIO switches between mono and speaker outputs (e.g. when pin 12 is connected to a
mechanical switch in the headphone socket to detect plug-in). The GPIOPOL bit reverses the
polarity of the CSB/GPIO input pin. In 3-wire control mode the GPIO pin can be use in the same
way.
Note that the speaker outputs and the mono output must be enabled for this function to work (see
Table 41). The GPIO has an internal de-bounce circuit when in this mode in order to prevent the
output enables from toggling multiple times due to input glitches. This de-bounce circuit is clocked
from a slow clock with period 221 x MCLK, enabled using the SLOWCLKEN register bit.
PP, Rev 3.3, December 2007
50
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
