Pre-Production
WM8940
REGISTER
ADDRESS
BIT
3:0
LABEL
PLLN[3:0]
DEFAULT
DESCRIPTION
REFER TO
1100
Integer (N) part of PLL input/output frequency ratio.
Use values greater than 5 and less than 13.
Master Clock and
Phase Locked
Loop (PLL)
37 (25h)
38 (26h)
39 (27h)
15:6
5:0
000h
Reserved
PLLK[23:18]
PLLK[17:9]
PLLK[8:0]
001100
Fractional (K) part of PLL1 input/output frequency ratio Master Clock and
(treat as one 24-digit binary number).
Reserved
Phase Locked
Loop (PLL)
15:9
8:0
00h
010010011 Fractional (K) part of PLL1 input/output frequency ratio Master Clock and
(treat as one 24-digit binary number).
Reserved
Phase Locked
Loop (PLL)
15:9
8:0
00h
011101001 Fractional (K) part of PLL1 input/output frequency ratio Master Clock and
(treat as one 24-digit binary number).
Phase Locked
Loop (PLL)
40 (28h)
41 (29h)
42 (2Ah)
15:0
15:0
15:2
1
0000h
0000h
0
Reserved
Reserved
Reserved
ALCZC
0 (zero
cross off)
ALC uses zero cross detection circuit.
0 = Disabled (recommended)
1 = Enabled
ALC Control 4
0
0
Reserved
43 (2Bh)
44 (2Ch)
15:0
15:9
8
0000h
00h
0
Reserved
Reserved
MBVSEL
Microphone Bias Voltage Control
0 = 0.9 * AVDD
Input Signal Path
1 = 0.75 * AVDD
Reserved
7:4
3
0h
0
AUXMODE
Auxiliary Input Mode
0 = inverting buffer
1 = mixer (on-chip input resistor bypassed)
Input Signal Path
Input Signal Path
2
AUX2INPPGA
0
Select AUX amplifier output as input PGA signal
source.
0=AUX not connected to input PGA
1=AUX connected to input PGA amplifier negative
terminal.
1
0
MICN2INPPGA
MICP2INPPGA
1
0
Connect MICN to input PGA negative terminal.
0=MICN not connected to input PGA
Input Signal Path
1=MICN connected to input PGA amplifier negative
terminal.
Connect input PGA amplifier positive terminal to MICP Input Signal Path
or VMID.
0 = input PGA amplifier positive terminal connected to
VMID
1 = input PGA amplifier positive terminal connected to
MICP through variable resistor string
45 (2Dh)
15:8
7
00h
0
Reserved
INPPGAZC
Input PGA zero cross enable:
Input Signal Path
Input Signal Path
0=Update gain when gain register changes
1=Update gain on 1st zero cross after gain register
write.
6
INPPGAMUTE
1
Mute control for input PGA:
0=Input PGA not muted, normal operation
1=Input PGA muted (and disconnected from the
following input BOOST stage).
Pre-Production, Rev 3.0, February 2007
75
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
