Pre-Production
WM8940
3-WIRE SERIAL CONTROL MODE
In 3-wire mode, every rising edge of SCLK clocks in one data bit from the SDIN pin. A rising edge on
CSB/GPIO latches in a complete control word consisting of the last 16 bits.
Figure 34 3-Wire Serial Control Interface
READBACK IN 3-WIRE MODE
The following two timing diagrams are also supported.
Figure 35 Alternative 3-Wire Serial Control Timing
Figure 36 Alternative 3-Wire Serial Control Timing
A limited number of Readback addresses are provided to enable ALC operation to be monitored and
to establish the identity and revision of the device.
REGISTER
ADDRESS
BIT
LABEL
CHIP_ID
DEFAULT
DESCRIPTION
Readback the CHIP ID
R0
15:0
Software Reset
R1
Power
2:0
DEVICE_REVI
SON
Readback the DEVICE_REVISON
Management 1
Table 56 Readback Registers
Pre-Production, Rev 3.0, February 2007
61
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
