Pre-Production
WM8940
Test Conditions
DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, TA=+25oC, Slave Mode, fs=48kHz, MCLK=256fs,
24-bit data, unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
FRAME propagation delay from BCLK falling edge
ADCDAT propagation delay from BCLK falling edge
DACDAT setup time to BCLK rising edge
DACDAT hold time from BCLK rising edge
tDL
10
15
ns
ns
ns
ns
tDDA
tDST
tDHT
10
10
AUDIO INTERFACE TIMING – SLAVE MODE
Figure 3 Digital Audio Data Timing – Slave Mode
Test Conditions
DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, TA=+25oC, Slave Mode, fs=48kHz, MCLK= 256fs,
24-bit data, unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
BCLK cycle time
tBCY
tBCH
tBCL
tLRSU
tLRH
tDH
81.38
32.55
32.55
10
ns
ns
ns
ns
ns
ns
ns
ns
BCLK pulse width high
BCLK pulse width low
FRAME set-up time to BCLK rising edge
FRAME hold time from BCLK rising edge
DACDAT hold time from BCLK rising edge
DACDAT set-up time to BCLK rising edge
ADCDAT propagation delay from BCLK falling edge
10
10
tDS
10
tDD
15
Note:
BCLK period should always be greater than or equal to MCLK period.
Pre-Production, Rev 3.0, February 2007
13
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
