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WM8912GEFL/RV 参数 Datasheet PDF下载

WM8912GEFL/RV图片预览
型号: WM8912GEFL/RV
PDF下载: 下载PDF文件 查看货源
内容描述: 超低功耗DAC与耳机驱动器的便携式音频应用 [Ultra Low Power DAC with Headphone Driver for Portable Audio Applications]
分类和应用: 驱动器便携式
文件页数/大小: 128 页 / 1259 K
品牌: WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
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Production Data  
WM8912  
The Charge Pump is enabled by setting the CP_ENA bit. When enabled, the charge pump adjusts  
the output voltages (CPVOUTP and CPVOUTN) as well as the switching frequency in order to  
optimise the power consumption according to the operating conditions. This can take two forms,  
which are selected using the CP_DYN_PWR register bit.  
Register control (CP_DYN_PWR = 0)  
Dynamic control (CP_DYN_PWR = 1)  
Under Register control, the HPOUTL_VOL, HPOUTR_VOL, LINEOUTL_VOL and LINEOUTR_VOL  
register settings are used to control the charge pump mode of operation.  
Under Dynamic control, the audio signal level in the DAC is used to control the charge pump mode of  
operation. This is the Wolfson ‘Class W’ mode, which allows the power consumption to be optimised  
in real time.  
Under the recommended usage conditions of the WM8912, the Charge Pump will be enabled by  
running the default headphone Start-Up sequence as described in the “Control Write Sequencer”  
section. (Similarly, it will be disabled by running the Shutdown sequence.) In these cases, the user  
does not need to write to the CP_ENA bit. The Charge Pump operating mode defaults to Register  
control; Dynamic control may be selected by setting the CP_DYN_PWR register bit, if appropriate.  
Note that the charge pump clock is derived from internal clock SYSCLK; this may derived from  
MCLK directly or else using the FLL output, as determined by the SYSCLK_SRC bit. Under normal  
circumstances an external clock signal must be present for the charge pump to function. However,  
the FLL has a free-running mode that does not require an external clock but will generate an internal  
clock suitable for running the charge pump. The clock division from SYSCLK is handled transparently  
by the WM8912 without user intervention, as long as SYSCLK and sample rates are set correctly.  
Refer to the “Clocking and Sample Rates” section for more detail on the FLL and clocking  
configuration.  
The Charge Pump control fields are described in Table 30.  
REGISTER  
ADDRESS  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
R98 (62h)  
0
CP_ENA  
0
Enable charge-pump digits  
0 = disable  
Charge  
Pump 0  
1 = enable  
R104 (68h)  
Class W (0)  
0
CP_DYN_PWR  
0
Enable dynamic charge pump power  
control  
0 = Charge pump controlled by  
volume register settings (Class G)  
1 = Charge pump controlled by real-  
time audio level (Class W)  
Class W is recommended for lowest  
power consumption  
Table 30 Charge Pump Control  
PD, Rev 4.0, September 2010  
47  
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