WM8904
Pre-Production
CHARGE PUMP
The WM8904 incorporates a dual-mode Charge Pump which generates the supply rails for the
headphone and line output drivers, HPOUTL, HPOUTR, and LINEOUTL and LINEOUTR. The Charge
Pump has a single supply input, CPVDD, and generates split rails CPVOUTP and CPVOUTN
according to the selected mode of operation. The Charge Pump connections are illustrated in Figure
39 (see the “Electrical Characteristics” section for external component values). An input decoupling
capacitor may also be required at CPVDD, depending upon the system configuration.
Figure 39 Charge Pump External Connections
The Charge Pump is enabled by setting the CP_ENA bit. When enabled, the charge pump adjusts the
output voltages (CPVOUTP and CPVOUTN) as well as the switching frequency in order to optimise
the power consumption according to the operating conditions. This can take two forms, which are
selected using the CP_DYN_PWR register bit.
Register control (CP_DYN_PWR = 0)
Dynamic control (CP_DYN_PWR = 1)
Under Register control, the HPOUTL_VOL, HPOUTR_VOL, LINEOUTL_VOL and LINEOUTR_VOL
register settings are used to control the charge pump mode of operation.
Under Dynamic control, the audio signal level in the DAC is used to control the charge pump mode of
operation. This is the Wolfson ‘Class W’ mode, which allows the power consumption to be optimised
in real time, but can only be used if the DAC is the only signal source. This mode should not be used
if any of the bypass paths are used to feed analogue inputs into the output signal path.
Under the recommended usage conditions of the WM8904, the Charge Pump will be enabled by
running the default headphone Start-Up sequence as described in the “Control Write Sequencer”
section. (Similarly, it will be disabled by running the Shutdown sequence.) In these cases, the user
does not need to write to the CP_ENA bit. The Charge Pump operating mode defaults to Register
control; Dynamic control may be selected by setting the CP_DYN_PWR register bit, if appropriate.
When digital sidetone is used (see “Digital Mixing”), it is recommended that the Charge Pump
operates in Register Control mode only (CP_DYN_PWR = 0). This is because the Dynamic Control
mode (Class W) does not measure the sidetone signal level and hence the Charge Pump
configuration cannot be optimised for all signal conditions when digital sidetone is enabled; this could
lead to signal clipping.
Note that the charge pump clock is derived from internal clock SYSCLK; this may be derived from
MCLK directly or else using the FLL output, as determined by the SYSCLK_SRC bit. Under normal
circumstances an external clock signal must be present for the charge pump to function. However,
the FLL has a free-running mode that does not require an external clock but will generate an internal
clock suitable for running the charge pump. The clock division from SYSCLK is handled transparently
by the WM8904 without user intervention, as long as SYSCLK and sample rates are set correctly.
Refer to the “Clocking and Sample Rates” section for more detail on the FLL and clocking
configuration.
PP, Rev 3.3, September 2012
84
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
