Pre-Production
WM8904
The polarity of each ADC output signal can be changed under software control using the
ADCL_DATINV and ADCR_DATINV register bits. The AIFADCL_SRC and AIFADCR_SRC register
bits may be used to select which ADC is used for the left and right digital audio interface data. These
register bits are described in Table 27.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R24 (18h)
Left Digital Audio interface source
7
AIFADCL_SRC
0
Audio
Interface 0
0 = Left ADC data is output on left
channel
1 = Right ADC data is output on left
channel
Right Digital Audio interface source
6
AIFADCR_SRC
1
0 = Left ADC data is output on right
channel
1 = Right ADC data is output on right
channel
R38 (26h)
Left ADC Invert
1
0
ADCL_DATINV
ADCR_DATINV
0
0
ADC Digital
0
0 = Left ADC output not inverted
1 = Left ADC output inverted
Right ADC Invert
0 = Right ADC output not inverted
1 = Right ADC output inverted
Table 27 ADC Routing and Control
The input data source for each DAC can be changed under software control using register bits
AIFDACL_SRC and AIFDACR_SRC. The polarity of each DAC input may also be modified using
register bits DACL_DATINV and DACR_DATINV. These register bits are described in Table 28.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R24 (18h)
Left DAC Invert
12
DACL_DATINV
0
Audio
Interface 0
0 = Left DAC output not inverted
1 = Left DAC output inverted
Right DAC Invert
11
5
DACR_DATINV
AIFDACL_SRC
AIFDACR_SRC
0
0
1
0 = Right DAC output not inverted
1 = Right DAC output inverted
Left DAC Data Source Select
0 = Left DAC outputs left interface data
1 = Left DAC outputs right interface data
Right DAC Data Source Select
0 = Right DAC outputs left interface data
4
1 = Right DAC outputs right interface
data
Table 28 DAC Routing and Control
PP, Rev 3.3, September 2012
63
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