Pre-Production
WM8850
PGA1 uses an internal zero cross detect circuit to ensure that all gain changes occur while the signal
passes through the zero point. This function eliminates any potential DC steps that can occur if gain
changes are applied at other times, and therefore the potential for zipper noise is removed. If no zero
cross occurs within a specified time after the gain change is requested via a register write a timeout
period will elapse and the gain will be changed regardless. This timeout period can be changed using
the vendor-specific PGA Control Verb:
SET VERB
BIT
BITFIELD
NAME
DEFAULT
DESCRIPTION
7B2h
7B3h
13:0
Terminal
Count
1FFFh
Set the period of the zero detect timeout clock:
0000h = Timeout disabled
0001h to 03FFh = Reserved
0400h = 1025 x 20.833µs (21.3ms)
0401h = 1026 x 20.833µs (21.4ms)
…
1FFFh = 8192 × 20.833µs (171ms)
…
3FFFh = 16384 × 20.833µs (341ms)
Note: The timeout clock uses the SYNC signal
from the HDA interface, so the absolute value
of the timeout period will depend on the
absolute accuracy of the SYNC signal.
ADC1 (NID = 02h)
Table 8 gives a summary of the ADC1 node:
NODE SUMMARY INFORMATION
02h
NID
Widget Type
Audio Input Converter
Supported Get Verbs
Supported Set Verbs
Unsolicited Responses
Vendor-Specific Verbs
Ah, F00h, F02h, F03h, F05h, F06h, F08h, F8Eh, FB1h
2h, 703h, 705h, 706h, 708h, 78Eh, 7B1h
Stream Drop
F8Eh, 78Eh : Unsolicited Response Priority Control Verb
FB1h, 7B1h : Channel Copy Verb
Table 8 ADC1 Node Summary Information
PP, April 2011, Rev 3.2
41
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
