Pre-Production
WM8850
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
Connection List Length Parameter (PID = 0Eh)
Bit
Bitfield Name
Rsvd
RW
R
Default
000000h
0
Description
[31:8]
[7]
Reserved
Long Form
R
Indicates that the connection list items are in short form
Indicates that there is 1 NID entry in the connection list
[6:0]
Connection List
Length
R
01h
Processing Capabilities Parameter (PID = 10h)
Bit
Bitfield Name
Rsvd
RW
R
Default
0000h
00h
Description
[31:16]
[15:8]
[7:1]
[0]
Reserved
NumCoeff
Rsvd
R
This widget does not support loadable coefficients
Reserved
R
00h
Benign
R
0
The “Processing Benign State” is not supported
GET CONNECTION LIST ENTRY VERB
Verb ID
Payload [7:0]
Response[31:0]
Get
F02h
00h
Bits [31:0] in the table below
Bit
Bitfield Name
RW
R
Default
00h
Description
[31:24]
[23:16]
[15:8]
[7:0]
Conn List Entry 3
Conn List Entry 2
Conn List Entry 1
Conn List Entry 0
Unused connection list entry
Unused connection list entry
Unused connection list entry
R
00h
R
00h
R
10h
Indicates that the S/PDIF Rx Input Widget node connects to the
SPDIF_IN Pin Widget (NID = 10h)
PROCESSING STATE VERB
Verb ID
F03h
Payload [7:0]
00h
Response[31:0]
Get
Set
Bits [31:0] in the table below
00000000h
703h
Bits [7:0] in the table below
Bit
Bitfield Name
Rsvd
RW
R
Default
000000h
00h
Description
[31:8]
[7:0]
Reserved
Processing State
RW
The processing block for the S/PDIF Rx widget node is SRC1. The
processing state is controlled as follows:
00h = Processing Off: SRC1 bypassed
01h = Processing On: SRC1 used
02h = Processing Off: SRC1 bypassed (benign not supported)
03h-7Fh = Reserved
80h-FFh = Vendor Specific – not used
Note:
The Processing State Verb should be set to 00h (SRC1 bypassed) when Software Formatted S/PDIF is selected or when any
S/PDIF Rx to DAC internal path is enabled. This is not done automatically.
PP, April 2011, Rev 3.2
115
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
