Product Preview
WM8816
ELECTRICAL CHARACTERISTICS
TEST CONDITIONS
AVDD=5.0V, AGND = 0V, TA = 25°C, unless otherwise stated.
PARAMETER
Analogue Inputs / Outputs
Input resistance
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RIN
CIN
For any gain
For any gain
7
10
2
kΩ
pF
Input capacitance
Op-amp gain = -15.5
Op-amp gain = 1
Op-amp gain = 15.5
From AVDD / AGND
From AVDD
0.8
3
mV
mV
mV
mA
dB
Input offset voltage (note 1)
Voffset
12
2.5
80
Supply current
IDD
5
Power supply rejection ratio
(Note 2)
PSRR
Gain Control
Gain range
G
D
-111.5
+15.5
0.5
dB
dB
dB
Gain step size
Gain error (Note 2)
0.5
DE
Lowest gains
guaranteed by
design, not tested in
production.
Gain match error (Note 2)
Mute attenuation
ME
Between channels
0.2
13
dB
dB
MATT
113
Audio Performance
Noise (Note 2)
Gain = 0dB
Gain = -60dB
V
IN = 0V, VOUT with OP275,
N
4
µVrms
A-weighed
Gain = mute
2.5
Total Harmonic Distortion plus
Noise
VIN= 1Vrms, gain=0dB,
THD+N
V
OUT with OP275,
DC to 20 kHz
0.001
(100)
130
%
(dB)
dB
Dynamic Range (Note 2)
Crosstalk (Note 2)
DNR
CR
120
Between channels,
gain=0dB, fIN=1kHz
-100
-110
dB
Digital Inputs / Outputs
Input low voltage
VIL
VIH
All digital inputs
All digital inputs
0.3 DVDD
0.4
V
V
V
V
Input high voltage
0.7 DVDD
DVDD -0.4
Output low voltage
VOL
VOH
ILoad = 2mA
Output high voltage
Control Interface Timing
Clock Frequency
ILoad = 2mA
fCCLK
tWHC
tWLC
tRC
1
MHz
ns
Period of CCLK high
Period of CCLK low
Rise time of CCLK
VIH to VIH
VIL to VIL
VIL to VIH
VIH to VIL
500
500
ns
100
100
ns
Fall time of CCLK
tFC
ns
Hold time, CCLK high to CSB low
tHCSH
tSSLCH
20
ns
Setup time, CSB low to CCLK
high
100
ns
Setup time, valid DATA to CCLK
high
tSDCH
tHCHD
tDCLD
tDSZ
100
100
ns
ns
ns
ns
Hold time, CCLK high to invalid
DATA
Setup time, CCLK low to valid
DATA
Hold time, CSB high or 16th
CCLK low to invalid DATA
Load = 100pF
200
200
Load = 3.3kΩ
20
PP Rev 1.5 October 2004
5
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
