Production Data
WM8783
AUDIO INTERFACE TIMING
LRCLK (input)
BCLK (see note)
ADCDAT (output)
tDD
Note – BCLK is generated internally to the WM8783, and is synchronised to LRCLK
Figure 3 Audio Interface Timing
Test Conditions
AVDD = 3.3V, GND = 0V, TA = +25oC.
PARAMETER
Audio Interface Timing
SYMBOL
MIN
TYP
MAX
UNIT
ADCDAT propagation delay from BCLK falling edge
tDD
20
ns
Figure 4 Recommended LRCLK Transition Area for Optimum Performance
It is recommended that for optimum performance the LRCLK transition occurs during the MCLK low,
as shown in Figure 4 above.
PD, August 2010, Rev 4.0
9
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
