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WM8781GEDS 参数 Datasheet PDF下载

WM8781GEDS图片预览
型号: WM8781GEDS
PDF下载: 下载PDF文件 查看货源
内容描述: 24位, 192kHz立体声ADC [24-Bit, 192kHz Stereo ADC]
分类和应用:
文件页数/大小: 20 页 / 230 K
品牌: WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
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WM8781  
Production Data  
SIGNAL TIMING REQUIREMENTS  
SYSTEM CLOCK TIMING  
Figure 1 System Clock Timing Requirements  
Test Conditions  
DVDD = 3.3V, DGND = 0V, TA = +25oC.  
PARAMETER  
SYMBOL  
MIN  
TYP  
MAX  
UNIT  
System Clock Timing Information  
MCLK System clock pulse width high  
MCLK System clock pulse width low  
MCLK System clock cycle time  
MCLK duty cycle  
T
MCLKL 1  
ns  
ns  
1
1
T
MCLKH 1  
TMCLKY  
28  
ns  
TMCLKDS  
40:60  
60:40  
Table 1 Master Clock Timing Requirements  
AUDIO INTERFACE TIMING – MASTER MODE  
Figure 2 Digital Audio Data Timing – Master Mode (see Control Interface)  
Test Conditions  
DVDD = 3.3V, DGND = 0V, TA = +25oC, Master Mode, fs = 48kHz, MCLK = 384fs, 24-bit data, unless otherwise stated.  
PARAMETER  
SYMBOL  
MIN  
TYP  
MAX  
UNIT  
Audio Data Input Timing Information  
LRCLK propagation delay from BCLK falling edge  
DOUT propagation delay from BCLK falling edge  
tDL  
0
0
10  
10  
ns  
ns  
tDDA  
Table 2 Digital Audio Data Timing - Master Mode  
PD, April 2006, Rev 4.1  
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