WM8778
Production Data
PIN DESCRIPTION
PIN
1
NAME
AINL
TYPE
DESCRIPTION
Analogue Input
Digital Output
Digital Output
Left channel input
2
ZFLAGR
ZFLAGL
DACBCLK
DACMCLK
DIN
Right channel zero flag output (external pull-up required)
Left channel zero flag output (external pull-up required)
3
4
Digital Input/Output DAC audio interface bit clock
5
Digital Input
Digital Input
Master DAC clock; 256, 384, 512 or 768fs (fs = word clock frequency)
DAC data input
6
7
DACLRC
ADCBCLK
ADCMCLK
DOUT
Digital Input/Output DAC left/right word clock
Digital Input/Output ADC audio interface bit clock
8
9
Digital Input
Master ADC clock; 256, 384, 512 or 768fs (fs = word clock frequency)
ADC data output
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Digital Output
ADCLRC
DGND
Digital Input/Output ADC left/right word clock
Supply
Supply
Digital negative supply
DVDD
Digital positive supply
MODE
Digital Input
Digital Input
Control interface mode select, tri-level
Serial interface Latch signal
CE\I2S
DI\DEEMPH
CL\IWL
Digital Input/Output Serial interface data
Digital Input
Serial interface clock
VOUTL
Analogue Output DAC channel left output
VOUTR
Analogue Output DAC channel right output
VMIDDAC
DACREFN
DACREFP
VMIDADC
ADCREFGND
ADCREFP
AVDD
Analogue Output DAC midrail decoupling pin ; 10uF external decoupling
Analogue Input
Analogue Input
DAC negative reference input
DAC positive reference input
Analogue Output ADC midrail divider decoupling pin; 10uF external decoupling
Analogue Output ADC reference buffer decoupling pin; 10uF external decoupling
Analogue Output ADC positive reference decoupling pin; 10uF external decoupling
Supply
Supply
Analogue positive supply
AGND
Analogue negative supply and substrate connection
Right channel input
AINR
Analogue Input
Note : Digital input pins have Schmitt trigger input buffers.
PD Rev 4.0 April 2005
4
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