WM8766
Preliminary Technical Data
PIN DESCRIPTION – 28 PIN SSOP
PIN
NAME
TYPE
DESCRIPTION
1
MODE
Digital input
Control format selection
0 = Software control
1 = Hardware control
2
3
MCLK
BCLK
LRCLK
DVDD
DGND
DIN1
Digital input
Master clock; 128, 192, 256, 384, 512 or 768fs (fs = word clock frequency)
Digital input/output Audio interface bit clock
Digital input/output Audio left/right word clock
4
5
Supply
Supply
Digital positive supply
6
Digital negative supply
7
Digital input
Digital input
Digital input
Do not connect
Digital input
DAC channel 1 data input
8
DIN2
DAC channel 2 data input
9
DIN3
DAC channel 3 data input
10
11
DNC
Do not connect
ML/I2S
Software Mode: Serial interface Latch signal
Hardware Mode: Input Audio Data Format
Software Mode: Serial control interface clock
Hardware Mode: Audio data input word length
Software Mode: Serial interface data
Hardware Mode: De-emphasis selection
12
13
MC/IWL
MD/DM
Digital input
Digital input
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
MUTE
TESTREF
VREFN
VREFP
VMID
Digital input/output DAC Zero Flag output or DAC mute input
Digital input
Supply
Test reference
DAC negative supply
Supply
DAC positive reference supply
Midrail divider decoupling pin; 10uF external decoupling
No internal connection
Analogue output
No connect
NC
NC
No connect
No internal connection
VOUT1L
VOUT1R
VOUT2L
VOUT2R
VOUT3L
VOUT3R
AGND
Analogue output
Analogue output
Analogue output
Analogue output
Analogue output
Analogue output
Supply
DAC channel 1 left output
DAC channel 1 right output
DAC channel 2 left output
DAC channel 2 right output
DAC channel 3 left output
DAC channel 3 right output
Analogue negative supply and substrate connection
Analogue positive supply
AVDD
Supply
Note: Digital input pins have Schmitt trigger input buffers.
PTD Rev 2.3 February 2004
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
