Production Data
WM8766
DIGITAL AUDIO INTERFACE – SLAVE MODE
BCLK
WM8766
DAC
DSP/
DECODER
LRCLK
DIN1/2/3
3
Figure 4 Audio Interface – Slave Mode
tBCH
tBCL
BCLK
LRCLK
tBCY
tLRSU
tDS
tLRH
DIN1/2/3
Figure 5 Digital Audio Data Timing – Slave Mode
Test Conditions
AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs unless otherwise
stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
BCLK cycle time
tBCY
tBCH
tBCL
50
20
20
10
ns
ns
ns
ns
BCLK pulse width high
BCLK pulse width low
LRCLK set-up time to BCLK
rising edge
tLRSU
LRCLK hold time from
BCLK rising edge
tLRH
tDS
10
10
10
ns
ns
ns
DIN1/2/3 set-up time to
BCLK rising edge
DIN1/2/3 hold time from
BCLK rising edge
tDH
Table 3 Digital Audio Data Timing – Slave Mode
PD Rev 4.1 July 2005
9
w
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